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Intel(R) 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR
Datasheet
January 2002
Document Number: 290725-002
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 845 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2 2 I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
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Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel , Pentium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2001-2002, Intel Corporation
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Intel 82845 MCH for SDR Datasheet
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Contents
1 Introduction ........................................................................................................................11 1.1 1.2 1.3 1.4 Terminology and Notations ...................................................................................11 Reference Documents ..........................................................................................13 (R) Intel 845 Chipset System Architecture ................................................................14 (R) Intel 82845 MCH Overview .................................................................................14 1.4.1 System Bus Interface ............................................................................15 1.4.2 System Bus Error Checking ..................................................................15 1.4.3 System Memory Interface .....................................................................16 1.4.4 AGP Interface........................................................................................16 1.4.5 Hub Interface.........................................................................................17 (R) 1.4.6 Intel MCH Clocking ..............................................................................17 1.4.7 System Interrupts ..................................................................................18 1.4.8 Powerdown Flow ...................................................................................18 System Bus Signals ..............................................................................................21 SDR SDRAM Interface Signals.............................................................................23 Hub Interface Signals............................................................................................23 AGP Interface Signals...........................................................................................24 2.4.1 AGP Addressing Signals .......................................................................24 2.4.2 AGP Flow Control Signals .....................................................................25 2.4.3 AGP Status Signals ...............................................................................25 2.4.4 AGP Strobes Signals.............................................................................26 2.4.5 AGP/PCI Signals ...................................................................................26 Clocks, Reset, and Miscellaneous Signals ...........................................................28 Voltage Reference and Power Signals .................................................................29 Reset States During Reset ...................................................................................30
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Signal Description..............................................................................................................19 2.1 2.2 2.3 2.4
2.5 2.6 2.7 3
Register Description ..........................................................................................................31 3.1 3.2 Register Terminology............................................................................................31 PCI Bus Configuration Space Access...................................................................32 3.2.1 Standard PCI Bus Configuration Mechanism........................................33 3.2.2 Routing Configuration Accesses ...........................................................33 I/O Mapped Registers ...........................................................................................34 3.3.1 CONF_ADDR--Configuration Address Register ..................................34 3.3.2 CONF_DATA--Configuration Data Register.........................................36 Memory-Mapped Register Space .........................................................................36 3.4.1 DRAMWIDTH--DRAM Width Register.................................................37 3.4.2 DQCMDSTR--Strength Control Register (SDQ and CMD Signal Groups) ......................................................................................38 3.4.3 CKESTR--Strength Control Register (SCKE Signal Group) ................39 3.4.4 CSBSTR--Strength Control Register (SCS# Signal Group).................40 3.4.5 CKSTR--Strength Control Register (Clock Signal Group) ...................41 3.4.6 RCVENSTR--Strength Control Register (RCVENOUT Signal Group) ........................................................................................42
3.3
3.4
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Host-Hub Interface Bridge Device Registers (Device 0)......................................43 3.5.1 VID--Vendor Identification Register (Device 0) ....................................45 3.5.2 DID--Device Identification Register (Device 0).....................................45 3.5.3 PCICMD--PCI Command Register (Device 0) .....................................46 3.5.4 PCISTS--PCI Status Register (Device 0).............................................47 3.5.5 RID--Revision Identification Register (Device 0)..................................48 3.5.6 SUBC--Sub-Class Code Register (Device 0).......................................48 3.5.7 BCC--Base Class Code Register (Device 0)........................................48 3.5.8 MLT--Master Latency Timer Register (Device 0) .................................49 3.5.9 HDR--Header Type Register (Device 0) ..............................................49 3.5.10 APBASE--Aperture Base Configuration Register (Device 0) ...............50 3.5.11 SVID--Subsystem Vendor Identification (Device 0) .............................51 3.5.12 SID--Subsystem Identification (Device 0) ............................................51 3.5.13 CAPPTR--Capabilities Pointer (Device 0) ............................................51 3.5.14 AGPM--AGP Miscellaneous Configuration Register (Device 0)...........52 3.5.15 DRB[0:7]--DRAM Row Boundary Registers (Device 0)........................52 3.5.16 DRA--DRAM Row Attribute Registers (Device 0) ................................53 3.5.17 DRT--DRAM Timing Register (Device 0) .............................................55 3.5.18 DRC--DRAM Controller Mode Register (Device 0) ..............................56 3.5.19 DERRSYN--DRAM Error Syndrome Register (Device 0) ....................58 3.5.20 EAP--Error Address Pointer Register (Device 0) .................................58 3.5.21 PAM[0:6]--Programmable Attribute Map Registers (Device 0) ...........59 3.5.22 FDHC--Fixed DRAM Hole Control Register (Device 0)........................62 3.5.23 SMRAM--System Management RAM Control Register (Device 0) ......63 3.5.24 ESMRAMC--Extended System Mgmt RAM Control Register (Device 0)................................................................................64 3.5.25 ACAPID--AGP Capability Identifier Register (Device 0).......................65 3.5.26 AGPSTAT--AGP Status Register (Device 0) .......................................66 3.5.27 AGPCMD--AGP Command Register (Device 0)..................................67 3.5.28 AGPCTRL--AGP Control Register (Device 0)......................................68 3.5.29 APSIZE--Aperture Size (Device 0) .......................................................69 3.5.30 ATTBASE--Aperture Translation Table Base Register (Device 0).......70 3.5.31 AMTT--AGP Interface Multi-Transaction Timer Register (Device 0) ...71 3.5.32 LPTT--AGP Low Priority Transaction Timer Register (Device 0).........72 3.5.33 TOM--Top of Low Memory Register (Device 0) ...................................73 3.5.34 MCHCFG--MCH Configuration Register (Device 0).............................74 3.5.35 ERRSTS--Error Status Register (Device 0) .........................................75 3.5.36 ERRCMD--Error Command Register (Device 0) .................................76 3.5.37 SMICMD--SMI Command Register (Device 0) ....................................78 3.5.38 SCICMD--SCI Command Register (Device 0) .....................................78 3.5.39 SKPD--Scratchpad Data Register (Device 0) ......................................79 3.5.40 CAPID--Product Specific Capability Identifier Register (Device 0) ......79 Bridge Registers (Device 1) ..................................................................................80 3.6.1 VID1--Vendor Identification Register (Device 1) ..................................81 3.6.2 DID1--Device Identification Register (Device 1)...................................81 3.6.3 PCICMD1--PCI-PCI Command Register (Device 1)............................82 3.6.4 PCISTS1--PCI-PCI Status Register (Device 1)....................................83 3.6.5 RID1--Revision Identification Register (Device 1)................................84 3.6.6 SUBC1--Sub-Class Code Register (Device 1).....................................84 3.6.7 BCC1--Base Class Code Register (Device 1)......................................84 3.6.8 MLT1--Master Latency Timer Register (Device 1) ...............................85 3.6.9 HDR1--Header Type Register (Device 1) ............................................85 3.6.10 PBUSN1--Primary Bus Number Register (Device 1) ...........................85
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3.6.11 3.6.12 3.6.13 3.6.14 3.6.15 3.6.16 3.6.17 3.6.18 3.6.19 3.6.20 3.6.21 3.6.22 3.6.23 3.6.24 4
SBUSN1--Secondary Bus Number Register (Device 1) ......................86 SUBUSN1--Subordinate Bus Number Register (Device 1)..................86 SMLT1--Secondary Master Latency Timer Register (Device 1) .........87 IOBASE1--I/O Base Address Register (Device 1) ...............................88 IOLIMIT1--I/O Limit Address Register (Device 1) ................................88 SSTS1--Secondary PCI-PCI Status Register (Device 1) .....................89 MBASE1--Memory Base Address Register (Device 1) ........................90 MLIMIT1--Memory Limit Address Register (Device 1) .........................90 PMBASE1--Prefetchable Memory Base Address Register (Device 1)................................................................................91 PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1)................................................................................91 BCTRL1--PCI-PCI Bridge Control Register (Device 1) ........................92 ERRCMD1--Error Command Register (Device 1) ...............................93 DWTC--DRAM Write Thermal Management Control Register (Device 1)................................................................................94 DRTC--DRAM Read Thermal Management Control Register (Device 1)................................................................................95
System Address Map.........................................................................................................97 4.1 Memory Address Ranges .....................................................................................97 4.1.1 VGA and MDA Memory Space..............................................................99 4.1.2 PAM Memory Spaces..........................................................................100 4.1.3 ISA Hole Memory Space .....................................................................100 4.1.4 TSEG SMM Memory Space ................................................................101 4.1.5 IOAPIC Memory Space .......................................................................101 4.1.6 System Bus Interrupt APIC Memory Space ........................................101 4.1.7 High SMM Memory Space...................................................................101 4.1.8 AGP Aperture Space (Device 0 BAR) .................................................102 4.1.9 AGP Memory and Prefetchable Memory.............................................102 4.1.10 Hub Interface Subtractive Decode ......................................................102 AGP Memory Address Ranges...........................................................................102 4.2.1 AGP DRAM Graphics Aperture ...........................................................103 System Management Mode (SMM) Memory Range...........................................103 4.3.1 SMM Space Definition .........................................................................104 4.3.2 SMM Space Restrictions .....................................................................104 I/O Address Space..............................................................................................105 (R) Intel MCH Decode Rules and Cross-Bridge Address Mapping.........................105 4.5.1 Hub Interface Decode Rules ...............................................................105 4.5.2 AGP Interface Decode Rules ..............................................................106 System Bus .........................................................................................................107 5.1.1 Dynamic Bus Inversion........................................................................107 5.1.2 System Bus Interrupt Delivery .............................................................108 5.1.3 Upstream Interrupt Messages .............................................................108 System Memory Interface ...................................................................................109 5.2.1 Single Data Rate (SDR) SDRAM Interface Overview .........................109 5.2.2 Memory Organization and Configuration.............................................109 5.2.2.1 Configuration Mechanism For DIMMs ...............................110 5.2.3 Memory Address Translation and Decoding .......................................111 5.2.4 DRAM Performance Description .........................................................112 5.2.4.1 Data Integrity (ECC)...........................................................112
4.2 4.3
4.4 4.5
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Functional Description .....................................................................................................107 5.1
5.2
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AGP Interface Overview .....................................................................................112 5.3.1 AGP Target Operations.......................................................................112 5.3.2 AGP Transaction Ordering ..................................................................114 5.3.3 AGP Signal Levels...............................................................................114 5.3.4 4x AGP Protocol..................................................................................114 5.3.5 Fast Writes ..........................................................................................114 5.3.6 AGP FRAME# Transactions on AGP ..................................................115 Power and Thermal Management ......................................................................117 5.4.1 Processor Power State Control ...........................................................117 5.4.2 Sleep State Control .............................................................................118 (R) Intel MCH Clocking ...........................................................................................118 (R) Intel MCH System Reset and Power Sequencing.............................................118
Electrical Characteristics .................................................................................................119 6.1 6.2 6.3 6.4 Absolute Maximum Ratings ................................................................................119 Power Characteristics .........................................................................................119 Signal Groups .....................................................................................................120 DC Characteristics ..............................................................................................122
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Ballout and Package Information.....................................................................................125 7.1 Package Mechanical Information........................................................................134
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Testability.........................................................................................................................137 8.1 8.2 XOR Test Mode Initialization ..............................................................................137 XOR Chains ........................................................................................................138
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Figures
Figure 1. Intel MCH Simplified Block Diagram.................................................................20 Figure 2. PAM Register Attributes .....................................................................................60 Figure 3. Addressable Memory Space ..............................................................................97 Figure 4. DOS Compatible Area Address Map..................................................................98 Figure 5. Extended Memory Range Address Map ............................................................98 (R) Figure 6. Intel 82845 MCH Ballout Diagram (Top View--Left Side) ..............................126 (R) Figure 7. Intel 82845 MCH Ballout Diagram (Top View--Right Side)............................127 (R) Figure 8. Intel MCH FC-BGA Package Dimensions (Top and Side View).....................134 (R) Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View)...............................135 Figure 10. XOR Tree Chain.............................................................................................137
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Tables
Table 1. General Terminology ...........................................................................................11 Table 2. Data Type Notation..............................................................................................12 Table 3. Number Format Notation .....................................................................................12 Table 4. Memory Capacity.................................................................................................16 (R) Table 5. Intel MCH Clock Ratio Table .............................................................................17 (R) Table 6. Intel MCH Internal Device Assignments ............................................................32 Table 7. Memory-mapped Register Address Map.............................................................36 (R) Table 8. Intel MCH Configuration Space (Device 0) ........................................................43 Table 9. PAM Register Attributes ......................................................................................61 (R) Table 10. Intel MCH Configuration Space (Device 1) ......................................................80 Table 11. SMM Space Address Ranges .........................................................................104 Table 12. Supported DIMM Configurations .....................................................................109 Table 13. Data Bytes on DIMM Used for Programming DRAM Registers ......................110 Table 14. Address Translation and Decoding .................................................................111 (R) Table 15. AGP Commands Supported by the Intel MCH When Acting as an AGP Target .................................................................................................113 Table 16. Data Rate Control Bits .....................................................................................115 (R) Table 17. PCI Commands Supported by the Intel MCH (When Acting as a FRAME# Target) ......................................................................................115 Table 18. Absolute Maximum Ratings.............................................................................119 Table 19. Power Characteristics......................................................................................119 Table 20. Signal Groups ..................................................................................................120 Table 21. DC Characteristics...........................................................................................122 (R) Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name ....................128 Table 23. XOR Chain 0 ...................................................................................................138 Table 24. XOR Chain 1 ...................................................................................................140 Table 25. XOR Chain 2 ...................................................................................................141 Table 26. XOR Chain 3 ...................................................................................................142 Table 27. XOR Chain 4 ...................................................................................................143 Table 28. XOR Chain 5 ...................................................................................................144 Table 29. XOR Chain 6 ...................................................................................................146 Table 30. XOR Chain 7 ...................................................................................................147
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Revision History
Revision Number -001 -002 Initial Release. * Changed the document name to add the term "for SDR". * DWTC--DRAM Write Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. * DRTC--DRAM Read Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. Description Date September 2001 January 2002
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Intel(R) 82845 MCH Features
! Intel(R) Pentium(R) 4 Processor (478 pin package)
Support Enhanced Mode Scaleable Bus Protocol 2x Address, 4x Data System Bus interrupt delivery 400 MHz system bus System Bus Dynamic Bus Inversion (DBI) 32-bit system bus addressing 12 deep In-Order Queue AGTL+ bus driver technology with integrated AGTL+ termination resistors System Memory Support Directly supports one SDR SDRAM channel, 64 bits wide (72 bits with ECC) 133 MHz Single Data Rate (SDR) SDRAM devices 64 Mb, 128 Mb, 256 Mb and 512 Mb technologies for x8 and x16 devices By using 64 Mb technology, the smallest memory capacity possible is 32 MB Configurable optional ECC operation (single bit Error Correction and multiple bit Error Detection) Page sizes of 2 KB, 4 KB, 8 KB and 16 KB (individually selected for every row) Thermal management Maximum of 3 Double-Sided DIMMs (6 rows populated) with unbuffered PC133 (with or without ECC) Note: Mixed mode, populating ECC and Non-ECC Memories simultaneously is not supported. 3 GB Maximum using 512 Mb technology Supports up to 24 simultaneous open pages Maximum memory bandwidth of 1.067 GB/s with PC133 Hub Interface to Intel(R) 82801BA ICH2 266 MB/s point-to-point hub interface to ICH2 66 MHz base clock MSI interrupt messages, power management state change, SMI, SCI and SERR error indication
! Accelerated Graphics Port (AGP) Interface
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Supports a single AGP device (either a connector or on the motherboard) Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol Supports only 1.5 V AGP electrical characteristics 32 deep AGP request queue Delayed transaction support for AGP-toSystem Memory FRAME# semantic reads System Interrupt Support System bus interrupt delivery mechanism Interrupts signaled as upstream memory writes from AGP/PCI Supports peer MSI between hub interface and AGP Provides redirection for IPI and upstream interrupts to the system bus Power Management SMRAM space remapping to A0000h Supports extended SMRAM space above 256 MB, additional TSEG from Top of Memory SMRAM accesses from AGP or hub interface are not supported PC '99 suspend to DRAM support ACPI, Revision 1.0b compliant power management APM, Revision 1.2 compliant power management NT Hardware Design Guide, Version 1.0 compliant Package MCH: 593 pin FC-BGA (37.5 x 37.5 mm)
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System Block Diagram
Intel (R) Pentium (R) 4 Processor
Intel (R) 845 Chipset System Memory 4x AGP Graphics Controller Intel (R) 82845 Memory Controller Hub (MCH) SDRAM Interface
AGP 2.0
SDRAM
Hub Interface 2 IDE Drives UltraATA/100 PCI Bus 4 USB Ports; 2 HC PCI Agent PCI Slots
AC '97 Codec(s) (optional)
AC'97 2.1
Intel (R) 82801BA I/O Controller Hub (ICH2)
LPC I/F LAN Connect
Super I/O
Keyboard, Mouse, FD, PP, SP, IR
GPIO
FW H Flash BIOS
sys_blk
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Introduction
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1
Introduction
The Intel(R) 82845 Memory Controller Hub (MCH) is designed for use with the Intel(R) Pentium(R) 4 processor in the 478-pin package. The Intel(R) 845 chipset contains two main components: the 82845 Memory Controller Hub (MCH) for the host bridge and the Intel 82801BA I/O Controller Hub (ICH2) for the I/O subsystem. The MCH provides the processor interface, system memory interface, AGP interface, and hub interface in an 845 chipset desktop platform. This document describes the 82845 Memory Controller Hub (MCH) for use with SDR (Single Data Rate) memory devices. Section 1.3 provides an overview of the 845 chipset.
1.1
Terminology and Notations
This section provides the definitions of some of the terms used in this document. Notations used for data types and numbers are also included. In addition, Section 3.1 contains register terminology definitions.
Table 1. General Terminology
Term MCH Description The Memory Controller Hub component that contains the processor interface, System Memory DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH2) and other IO controller hubs over proprietary interconnect called the hub interface. The I/O Controller Hub component that contains the primary PCI interface, LPC interface, USB, ATA-100, AC '97, and other I/O functions. It communicates with the MCH over a proprietary interconnect called the hub interface. This term is used synonymously with processor. The internal base logic in the MCH. Processor-to-MCH interface. The system bus runs at 400 MHz, from a 100 MHz quadpumped clock. It consists of source synchronous transfers for address and data, and system bus interrupt delivery. The proprietary hub interconnect that connects the MCH to the ICH2. In this document hub interface cycles originating from or destined for the primary PCI interface on the ICH2 are generally referred to as hub interface cycles. Refers to the AGP interface that is in the MCH. The MCH supports AGP 2.0 compliant components only with 1.5 V signaling level. PIPE# and SBA addressing cycles and their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP bus are generally referred to as AGP/PCI transactions. The physical PCI bus, driven directly by the ICH2 component. It supports 5 V, 32-bit, 33 MHz PCI 2.2 compliant components. Communication between PCI_A and the MCH occurs over the hub interface. Note: Even though this PCI bus is referred to as PCI_A, it is not PCI Bus #0 from a configuration standpoint. Full Reset A full MCH reset is defined in this document when RSTIN# is asserted.
ICH2
Host Core System Bus
Hub Interface
Accelerated Graphics Port (AGP) PCI_A
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Term GART GTLB UP DBI MSI IPI SDR
Description Graphics Aperture Re-map Table. This table contains the page re-map information used during AGP aperture address translations. Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries. Uni-Processor. Dynamic Bus inversion. Message Signaled Interrupts. MSIs allow a device to request interrupt service via a standard memory write transaction instead of through a hardware signal. Inter Processor Interrupt. Single Data-Rate SDRAM memory.
Table 2. Data Type Notation
Data Type bit (b) byte word DWord (DW) QWord (QW) DQWord (DQW) Smallest unit, 0 or 1 8 bits 16 bits = 2 bytes Doubleword: 32 bits = 4 bytes Quadword: 8 bytes = 4 words Double Quadword. 16 bytes or 8 words. This is sometimes referred to as a Superword (SW or SWord), and is also referred to as a "Cache Line". 1024 bytes 1, 048,576 bits = 128 KB 1,048,576 bytes = 1024 KB 1024 Mb 1024 MB Size
Kilobyte (KB) Megabit (Mb) Megabyte (MB) Gigabit (Gb) Gigabyte (GB)
Table 3. Number Format Notation
Number Format Decimal (default) Binary Hex b h Notation Example 14 1110b 0Eh
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1.2
Reference Documents
Document Intel(R) Pentium 4 Processor in a 478 Pin Package and Intel(R) 845 Chipset Platform for SDR Design Guide Intel(R) 82801BA I/O Controller Hub (ICH2) and Intel(R) 82801BAM I/O Controller Hub (ICH2-M) Datasheet Intel(R) 845 Chipset Thermal and Mechanical Design Guidelines for SDR Intel 82802AB/AC Firmware Hub (FWH) Datasheet PCI Local Bus Specification, Revision 2.1 Accelerated Graphics Port Interface Specification, Revision 2.0 Intel Pentium 4 Processor Datasheet PC SDRAM Specification, Rev. 1.7 developer.intel.com
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Document Number / Location 298354 290687 298586 290658 Contact Intel Field Representative www.agpforum.org
Note: See the Intel(R) Pentium 4 Processor in a 478 Pin Package and Intel(R) 845 Chipset Platform Design Guide for an expanded set of related documents.
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1.3
Intel(R) 845 Chipset System Architecture
The MCH provides the processor interface, system memory interface, AGP interface, and hub interface in an 845 chipset desktop platform. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The MCH supports a single channel of PC133 SDRAM. The MCH contains advanced power management logic. The 845 chipset platform supports the I/O Controller Hub 2 (ICH2) to provide the features required by a desktop platform.
Intel 82801BA I/O Controller Hub 2 (ICH2)
The ICH2 is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI Bus and integrates many of the functions needed in today's PC platforms. The MCH and ICH2 communicate over a dedicated hub interface. The 82801BA ICH2 Functions and capabilities include: * PCI Rev 2.2 compliant with support for 33 MHz PCI operations * Supports up to 6 Request/Grant pairs (PCI slots) * Power management logic support * Enhanced DMA controller, interrupt controller, and timer functions * Integrated IDE controller; Ultra ATA/100/66/33 * USB host interface; 2 host controllers and supports 4 USB ports * Integrated LAN controller * System Management Bus (SMBus) compatible with most I2C devices; ICH2 has both bus master and slave capability * AC '97 2.1 compliant link for audio and telephony codecs; up to 6 channels (ICH2) * Low Pin Count (LPC) interface * FWH Interface (FWH Flash BIOS support) * Alert on LAN* (AOL and AOL2)
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1.4
Intel(R) 82845 MCH Overview
The MCH role in a system is to manage the flow of information between its four interfaces: the system bus, the memory interface, the AGP port, and the hub interface. The MCH arbitrates between the four interfaces, when each initiates an operation. While doing so, the MCH supports data coherency via snooping and performs address translation for access to AGP Aperture memory. To increase system performance, the MCH incorporates several queues and a write cache. The MCH is in a 593 pin FC-BGA package and contains the following functionality: * Supports single Pentium 4 processor configuration at 400 MHz * AGTL+ system bus with integrated termination supporting 32-bit system bus addressing * Up to 3 GB (w/ 512 Mb technology) of PC133 SDRAM * 1.5 V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability * 8 bit, 66 MHz 4x hub interface to the ICH2 * Distributed arbitration for highly concurrent operation
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1.4.1
System Bus Interface
The MCH is optimized for the Pentium 4 processor. The primary enhancements over the Compatible Mode P6 bus protocol are: * Source synchronous double-pumped address * Source synchronous quad-pumped data * System bus interrupt and side-band signal delivery The MCH supports a 64-byte cache line size. Only one processor is supported at a system bus frequency of 400 MHz. The MCH supports a 3:4 host-to-memory frequency ratio (using the 100 MHz clock). The MCH integrates AGTL+ termination resistors on all of the AGTL+ signals. The MCH supports 32-bit system bus addresses, allowing the processor to access the entire 4 GB of the MCH memory address space. The MCH has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the system bus. The MCH supports two outstanding defer cycles at a time; however, only one to any particular I/O interface. Processor-initiated I/O cycles are positively decoded to AGP/PCI or MCH configuration space and subtractively decoded to the hub interface. Processorinitiated memory cycles are positively decoded to AGP/PCI or system memory, and are again subtractively decoded to the hub interface, if under 4 GB. AGP semantic memory accesses initiated from AGP/PCI to system memory are not snooped on the system bus. Memory accesses initiated from AGP/PCI using PCI semantics and from the hub interface to system memory will be snooped on the system bus. Memory accesses whose addresses lie within the AGP aperture are translated using the AGP address translation table, regardless of the originating interface.
1.4.2
System Bus Error Checking
The MCH does not generate parity, nor check parity for data, address/request, and response signals on the processor bus.
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1.4.3
System Memory Interface
The MCH directly supports one channel of PC133 SDRAM. The memory interface supports Single Data Rate (SDR) devices with densities of 64 Mb, 128 Mb, 256 Mb, and 512 Mb technology. The memory interface also supports variable page sizes of 2 KB, 4 KB, 8 KB, and 16 KB. Page size is individually selected for every row and a maximum of 8 pages per DIMM may be opened simultaneously. The MCH supports a maximum of 3 double-sided DIMMs (6 rows populated) with unbuffered PC133 (with or without ECC) Note that in mixed mode, populating ECC and Non-ECC memories simultaneously is not supported.
Table 4. Memory Capacity
Technology 64 Mb 128 Mb 256 Mb 512 Mb SDR (PC133) Maximum 384 MB 768 MB 1.5 GB 3 GB
The memory interface provides optional ECC error checking for system memory data integrity. During system memory writes, ECC is generated on a QWord (64 bit) basis. Because the MCH stores only entire cache lines in its internal buffers, partial QWord writes initially cause a read of the underlying data, and their write-back into memory is no different from that of a complete cache line. During system memory reads, and the read of the data that underlies partial writes, the MCH supports detection of single-bit and multiple-bit errors, and will correct single-bit errors when correction is enabled. The MCH supports a thermal management scheme to selectively manage reads and/or writes. Thermal management can be triggered by preset read/write bandwidth limits.
1.4.4
AGP Interface
A single AGP component or connector (not both) is supported by the MCH AGP interface. The AGP buffers operate only in 1.5 V mode. They are not 3.3 V safe. The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to system memory are not snooped on the system bus. PCI semantic cycles to system memory are snooped on the system bus. The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. Both upstream and downstream addressing is limited to 32 bits for AGP and AGP/PCI transactions. The MCH contains a 32 deep AGP request queue. High-priority accesses are supported. All accesses from the AGP/PCI interface that fall within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked from a dedicated 66 MHz clock (66IN). The AGP-to-host/core interface is asynchronous.
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Introduction
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1.4.5
Hub Interface
The 8-bit hub interface connects the MCH to the ICH2. All communication between the MCH and the ICH2 occurs over the hub interface. The hub interface runs at 66 MHz / 266 MB/s. In addition to the normal traffic types, the following communication also occurs over the hub interface: * Interrupt related messages * Power management events as messages * SMI, SCI, and SERR error indication messages It is assumed that the hub interface is always connected to an ICH2.
1.4.6
Intel(R) MCH Clocking
The MCH has the following clock input pins: * Differential BCLK for the host interface * 66 MHz clock input for the AGP and hub interface Clock synthesizer chip(s) generate the system host clocks, AGP and hub interface clocks, and PCI clocks. The system bus target speed is 400 MHz. The MCH does not require any relationship between the HCLKIN host clock and the 66 MHz clock generated for AGP and the hub interface; they are asynchronous to each other. The AGP and hub interface runs at a constant 66 MHz base frequency. The hub interface runs at 4x. AGP transfers can be 1x, 2x, or 4x. Table 5 indicates the supported frequency ratios between the various interfaces.
Table 5. Intel MCH Clock Ratio Table
Interface Speed SDR 133 MHz 66 MHz 66 MHz Processor BCLK (100 MHz) 3:4 synchronous Asynchronous Asynchronous
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Memory AGP Hub interface
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1.4.7
System Interrupts
The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported. Intel 8259 support consists of flushing inbound hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub interface. The MCH supports the Pentium 4 processor interrupt delivery mechanism. IOxAPIC and PCI MSI interrupts are generated as memory writes. The MCH decodes upstream memory writes to the range 0FEE0_0000h-0FEEF_FFFFh from AGP and the hub interface as message-based interrupts. The MCH forwards the memory writes, along with the associated write data, to the system bus as an interrupt message transaction. Note that since this address does not decode as part of system memory, the write cycle and the write data are not forwarded to system memory via the write buffer. The MCH provides the response and TRDY# for all interrupt message cycles, including the ones originating from the MCH. The MCH supports interrupt re-direction for inter-processor interrupts (IPIs) as well as upstream interrupt memory writes. For message-based interrupts, system write-buffer coherency is maintained by relying on strict ordering of memory writes. The MCH ensures that all memory writes received from a given interface prior to an interrupt message memory write are delivered to the system bus for snooping in the same order that they occur on the given interface.
1.4.8
Powerdown Flow
Since the MCH is powered down during STR, the MCH cannot maintain any state information when exiting STR. Thus, the entire initialization process when exiting STR must be performed by the BIOS via accesses to the DRC2 register. Entry into STR (ACPI S3) is initiated by the Operating System (OS), based on detecting a lack of system activity. The OS unloads all system device drivers as part of the process of entering STR. The OS then writes to the PM1_CNT I/O register in the ICH2 to trigger the transition into STR.
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2
Signal Description
This chapter provides a detailed description of the MCH signals. The signal descriptions are arranged in functional groups according to their associated interface (see Figure 1). The states of all of the signals during reset are provided in the System Reset section. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I O I/O s/t/s as/t/s Input pin Output pin Bi-directional Input/Output pin Sustained Three-state. This pin is driven to its inactive state prior to threestating. Active Sustained Three-state. This applies to some of the hub interface signals. This pin is weakly driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal: AGTL+ AGP Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The MCH integrates AGTL+ termination resistors. AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. CMOS buffers. Voltage reference signal
CMOS Ref
Note: System address and data bus signals are logically inverted signals. In other words, the actual values are inverted of what appears on the system bus. This must be taken into account and the addresses and data bus signals must be inverted inside the MCH. All processor control signals follow normal convention. A "0" indicates an active level (low voltage) if the signal is followed by "#" symbol, and a "1" indicates an active level (high voltage) if the signal has no "#" suffix.
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Signal Description
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Figure 1. Intel MCH Simplified Block Diagram
HA[31:3]# HD[63:0]# ADS# BNR# BP RI# DBSY# DE FE R# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# CPURS T# BR0# DBI[3:0]# HADSTB[1:0]# HDS TB P[3:0]/HDSTBN[3:0] SBA[7:0] PIPE # ST[2:0] RBF# WBF# AD_STB[1:0], AD_STB [1:0]# SBSTB, SBSTB# AGPRCOM P G_FRAM E# G_IRDY# G_TRDY# G_S TO P# G_DEV SEL# G_REQ# G_G NT# G_A D[31:0] G_C/BE [3:0]# G_P AR HVREF SDREF HI_REF AGPREF HLRCOM P GRCOM P HRCOM P[1:0] HSW NG[1:0] SMRCOM P VCC1_5 VCC1_8 VCCSM VCCA[1:0] VTT VSS VSSA[1:0] BCLK, BCLK# 66IN SCK[11:0] RSTIN# TESTIN#
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P rocessor System B us Interface
AGP Interface
SCS[11:0]# SM A[12:0] SBS[1:0] SRAS# SCAS# SW E# SDQ[63:0] SCB[7:0] SCKE[5:0] RDCLKO RDCLK IN
System Mem ory SDRAM Interface Voltage Refernce, PLL Power
HI_[10:0] HI_S TB , HI_STB#
Hub Interface Clocks and Reset
block_dia_845
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2.1
System Bus Signals
Signal Name ADS# BNR# Type I/O AGTL+ I/O AGTL+ O AGTL+ Description Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. Block Next Request: BNR# is used to block the current request bus owner from issuing a new request. This signal dynamically controls the system bus pipeline depth. Bus Priority Request: The MCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The MCH pulls the processor bus BR0# signal low during CPURST#. The signal is sampled by the processor on the active-toinactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 BCLKs and the maximum hold time is 20 BCLKs. BR0# should be three-stated after the hold time requirement has been satisfied. Processor Reset: The CPURST# pin is an output from the MCH. The MCH asserts CPURST# while RSTIN# (PCIRST# from the ICH2) is asserted and for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the processor to begin execution in a known state. Data Bus Busy: DBSY# is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer Response: This signal, when asserted, indicates that the MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response. Dynamic Bus Inversion: DBI[3:0]# are driven along with the HD[63:0]# signals. DBI[3:0]# Indicate if the associated data signals are inverted. DBI[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DBI[x]# DBI3# DBI2# DBI1# DBI0# DRDY# HA[31:3]# I/O AGTL+ I/O AGTL+ Data Bits HD[63:48]# HD[47:32]# HD[31:16]# HD[15:0]#
BPRI#
BR0#
I/O AGTL+
CPURST#
O AGTL+
DBSY# DEFER#
I/O AGTL+ O AGTL+ I/O AGTL+
DBI[3:0]#
Data Ready: Asserted for each cycle that data is transferred. Host Address Bus: HA[31:3]# connect to the system address bus. During processor cycles, HA[31:3]# are inputs. The MCH drives HA[31:3]# during snoop cycles on behalf of the hub interface and AGP/Secondary PCI initiators. HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the system bus. Host Address Strobe: The source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. Strobe HADSTB0# HADSTB1# Address Bits HA[16:3]#, HREQ[4:0]# HA[31:17]#
HADSTB[1:0]#
I/O AGTL+
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Signal Name HD[63:0]#
Type I/O AGTL+ I/O AGTL+
Description Host Data: These signals are connected to the system data bus. HD[63:0]# are transferred at a 4x rate. Note that the data signals are inverted on the system bus. Differential Host Data Strobes: The differential source synchronous strobes used to transfer HD[63:0]# and DBI[3:0]# at the 4x transfer rate. Strobe HDSTBP3#, HDSTBN3# HDSTBP2#, HDSTBN2# HDSTBP1#, HDSTBN1# HDSTBP0#, HDSTBN0# Data Bits HD[63:48]#, DBI3# HD[47:32]#, DBI2# HD[31:16]#, DBI1# HD[15:0]#, DBI0#
HDSTBP[3:0]# HDSTBN[3:0]#
HIT#
I/O AGTL+ I/O AGTL+
Hit: This signal indicates that a caching agent holds an unmodified version of the requested line. HIT# is also driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: This signal indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. HITM# is also driven in conjunction with HIT# to extend the snoop window. Host Lock: All system bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface or AGP snoopable access to system memory are allowed when HLOCK# is asserted by the processor). Host Request Command: These signals define the attributes of the request. In Enhanced Mode HREQ[4:0]# are transferred at 2x rate. HREQ[4:0]# are asserted by the requesting agent during both halves of Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the MCH host bridge are defined in the Section 5.1.
HITM#
HLOCK#
I AGTL+
HREQ[4:0]#
I/O AGTL+
HTRDY# RS[2:0]#
O AGTL+ O AGTL+
Host Target Ready: HTRDY# indicates that the target of the processor transaction is able to enter the data transfer phase. Response Status: RS[2:0]# indicates the type of response according to the following the table: RS[2:0] 000 001 010 011 100 101 110 111 Response Type Idle state Retry response Deferred response Reserved (not driven by MCH) Hard Failure (not driven by MCH) No data response Implicit Write back Normal data response
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2.2
SDR SDRAM Interface Signals
Signal Name SCS[11:0]# Type O CMOS Description Chip Select: These signals select the particular SDRAM components during the active state. Note: There are two SCS# signals per SDRAM row. These signals can be toggled on every rising system memory clock edge. SMA[12:0] SBS[1:0] O CMOS O CMOS O CMOS O CMOS O CMOS I/O CMOS I/O CMOS O CMOS Multiplexed Memory Address: These signals are used to provide the multiplexed row and column address to SDRAM. Memory Bank Select: SBS[1:0] define the banks that are selected within each SDRAM row. The SMA and SBS signals combine to address every possible location in a SDRAM device. SDRAM Row Address Strobe: SRAS# is Used with SCAS# and SWE# (along with SCS#) to define the DRAM commands. SDRAM Column Address Strobe: SCAS# is used with SRAS# and SWE# (along with SCS#) to define the SDRAM commands. Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#) to define the SDRAM commands. Data Lines: These signals are used to interface to the SDRAM data bus. Check Bit Data Lines: These signals are used to interface to the SDRAM ECC signals. Clock Enable: These pins are used to signal a self-refresh or Powerdown command to a SDRAM array when entering system suspend. SCKE is also used to dynamically powerdown inactive SDRAM rows. There is one SCKE per SDRAM row. These signals can be toggled on every rising SCLK edge. Clock Output: RDCLKO is used to emulate source-synch clocking for reads. This signal connects to RDCLKIN. Clock Input: RDCLKIN is used to emulate source-synch clocking for reads. This signal connects to RDCLKO.
SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] SCKE[5:0]
RDCLKO RDCLKIN
O CMOS I CMOS
2.3
Hub Interface Signals
Signal Name HI_[10:0] HI_STB HI_STB# Type I/O CMOS I/O CMOS I/O CMOS Description Hub Interface Signals: Signals used for the hub interface. Hub Interface Strobe: One of two differential strobe signals used to transmit or receive packet data over the hub interface. Hub Interface Strobe Compliment: One of two differential strobe signals used to transmit or receive packet data over the hub interface.
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2.4
2.4.1
AGP Interface Signals
AGP Addressing Signals
Signal Name PIPE# Type I AGP Description Pipelined Read: This signal is asserted by the AGP master to indicate a full-width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted. When PIPE# is deasserted, no new requests are queued across the AD bus. During SBA Operation: Not Used. During FRAME# Operation: Not Used. PIPE# is a sustained three-state signal from masters (graphics controller), and is an MCH input. Note: Initial AGP designs may not use PIPE# (i.e., PCI only 66 MHz). Therefore, an 8 k pull-up resistor connected to this pin is required on the motherboard. SBA[7:0] I AGP Sideband Address: These signals are used by the AGP master (graphics controller) to place addresses into the AGP request queue. The SBA bus and AD bus operate independently. That is, a transaction can proceed on the SBA bus and the AD bus simultaneously. During PIPE# Operation: Not Used. During FRAME# Operation: Not Used. Note: When sideband addressing is disabled, these signals are isolated (no external/internal pull-up resistors are required). NOTE: The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset.
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2.4.2
AGP Flow Control Signals
Signal Name RBF# Type I AGP Description Read Buffer Full: RBF# indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted, the MCH is not allowed to initiate the return low priority read data. That is, the MCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data, then it is not required to implement this signal. During FRAME# Operation: Not Used. WBF# I AGP Write-Buffer Full: Indicates if the master is ready to accept fast write data from the MCH. When WBF# is asserted, the MCH is not allowed to drive fast write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data, then it is not required to implement this signal. During FRAME# Operation: Not Used.
2.4.3
AGP Status Signals
Signal Name ST[2:0] Type O AGP Description Status: ST[2:0] provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its G_GNT# is asserted. When G_GNT# is deasserted, these signals have no meaning and must be ignored. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings. During FRAME# Operation: These signals are not used during FRAME#-based operation, except that a `111' indicates that the master may begin a FRAME# transaction.
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2.4.4
AGP Strobes Signals
Signal Name AD_STB0 Type I/O (s/t/s) AGP I/O (s/t/s) AGP I/O (s/t/s) AGP I/O (s/t/s) AGP I AGP I AGP Description Address/Data Bus Strobe-0: This signal provides timing for 2x and 4x data on AD[15:0] and the C/BE[1:0]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-0 Compliment: Differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-1: This signal provides timing for 2x- and 4xclocked data on AD[31:16] and C/BE[3:2]# signals. The agent that is providing the data drives this signal. Address/Data Bus Strobe-1 Compliment: The differential compliment to the AD_STB1 signal. It is used to provide timing for 4x-clocked data. Sideband Strobe: This signal provides timing for 2x- and 4x- clocked data on the SBA[7:0] bus. It is driven by the AGP master after the system has been configured for 2x- or 4x- clocked sideband address delivery. Sideband Strobe Compliment: SB_STB# is the differential compliment to the SB_STB signal. It is used to provide timing for 4x-clocked data.
AD_STB0#
AD_STB1
AD_STB1#
SB_STB
SB_STB#
2.4.5
AGP/PCI Signals
For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined below.
Signal Name G_FRAME# Type I/O s/t/s AGP I/O s/t/s AGP Description FRAME: During FRAME# Operations, G_FRAME# is an output when the MCH acts as an initiator on the AGP Interface. Initiator Ready#: This signal indicates the AGP compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred. Target Ready: This signal indicates the AGP compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. STOP: G_STOP Is an input when the MCH acts as a FRAME#-based AGP initiator and an output when the MCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface.
G_IRDY#
G_TRDY#
I/O s/t/s AGP
G_STOP#
I/O s/t/s AGP
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Signal Name G_DEVSEL#
Type I/O s/t/s AGP
Description Device Select: This signal indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The MCH asserts G_DEVSEL# based on the DRAM address range being accessed by a PCI initiator. As an input it indicates whether any device on the bus has been selected. Request: Indicates that a FRAME# or PIPE#-based AGP master is requesting use of the AGP interface. This signal is an input into the MCH. Grant: During SBA, PIPE# and FRAME# operation, G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Address/Data Bus: These signals are used to transfer both address and data on the AGP interface. Command/Byte Enable: During FRAME# Operation: During the address phase of a transaction, G_C/BE[3:0]# define the bus command. During the data phase, G_C/BE[3:0]# are used as byte enables. The byte enables determine which byte lanes carry meaningful data. During PIPE# Operation: When an address is enqueued using PIPE#, the G_C/BE# signals carry command information. The command encoding used during PIPE#-based AGP is DIFFERENT than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus).
G_REQ#
I AGP O AGP I/O AGP I/O AGP
G_GNT#
G_AD[31:0] G_C/BE[3:0]#
G_PAR
I/O AGP
Parity: During FRAME# Operations: This signal is driven by the MCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the MCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across AD[31:0] and G_C/BE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation.
NOTE: PCIRST# from the ICH2 is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also use PCIRST# provided by the ICH2 as an input to reset its internal logic.
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2.5
Clocks, Reset, and Miscellaneous Signals
Signal Name BCLK BCLK# 66IN Type I CMOS I CMOS Description Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the MCH logic that is in the host clock domain. 66 MHz Clock In: This pin receives a 66 MHz clock from the clock synthesizer. This clock is used by AGP/PCI and hub interface clock domains. Note: That this clock input is 3.3 V tolerant. SCK[11:0] RSTIN# O CMOS I CMOS System Memory Clocks (SDR): These signals deliver a synchronized clock to the DIMMs. There are two per row. Reset In: When asserted, this signal asynchronously resets the MCH logic. RSTIN# is connected to the PCIRST# output of the ICH2. All AGP/PCI output and bi-directional signals will also three-state compliant to PCI Rev 2.0 and 2.1 specifications. Note: This input needs to be 3.3 V tolerant. TESTIN# I CMOS Test Input: This pin is used for manufacturing and board level test purposes. Note: This signal has an internal pull-up resistor.
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2.6
Voltage Reference and Power Signals
Signal Name HVREF SDREF HI_REF AGPREF HLRCOMP Type Ref Ref Ref Ref I/O CMOS I/O CMOS I/O CMOS I CMOS I/O CMOS Description Host Reference Voltage: Reference voltage input for the data, address, and common clock signals of the host AGTL+ interface. SDRAM Reference Voltage: Reference voltage input for DQ, DQS, RDCLKIN (SDR). Hub Interface Reference: Reference voltage input for the hub interface. AGP Reference: Reference voltage input for the AGP interface. Compensation for Hub Interface: This signal is used to calibrate the hub interface I/O buffers. It is connected to a 40.2 pull-up resistor with 1% tolerance and is pulled up to VCC1_8. Compensation for AGP: This signal is used to calibrate buffers. It is connected to a 40.2 pull-down resistor with a 1% tolerance. Compensation for Host: These signals are used to calibrate the host AGTL+ I/O buffers. Each signal is connected to a 24.9 pull-down resistor with a 1% tolerance. Host Reference Voltage: Reference voltage input for the compensation logic. System Memory RCOMP: 1.5 V Power Input: These pins are connected to a 1.5 V power source. 1.8 V Power Input Pins: These pins are connected to a 1.8 V power source. SDRAM Power Input Pins: These pins are connected to a 3.3 V power source for SDR. PLL Power Input Pins: These pins provide power for the PLL. AGTL+ Bus Termination Voltage Inputs: These pins provide the AGTL+ bus termination. Ground: The VSS pins are the ground pins for the MCH. PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL on the MCH.
GRCOMP HRCOMP[1:0]
HSWNG[1:0] SMRCOMP VCC1_5 VCC1_8 VCCSM VCCA[1:0] VTT VSS VSSA[1:0]
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2.7
Reset States During Reset
Z ISO S H L D I Ti-state Isolate inputs in inactive state Strap input sampled during assertion or on the de-asserting edge of RSTIN# Driven high Driven low Strong drive (to normal value supplied by core logic if not otherwise stated) Input active
State During RSTIN# Assertion State During RSTIN# Assertion Z I State During RSTIN# Assertion Z Z I I Z Z Z/I Z/I Z/I Z/I Z/I Z Z
Signal Name
Signal Name
Signal Name
System Bus Interface CPURST# HADSTB[1:0]# AP[1:0]# HA[31:4]# HD[63:0]# HDSTBP[3:0]# HDSTBN[3:0]# DBI[3:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# BREQ0# HVREF L Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I Z/I I
HLRCOMP HSWNG
AD_STB[1:0] AD_STB[1:0]# SB_STB SB_STB# G_AD[31:0] G_C/BE[3:0]# G_FRAME# G_IRDY# G_TRDY# G_STOP# G_DEVSEL# G_PAR AGPREF Hub Interface HI_[10:0] HI_STB
SDR System Memory SCK[11:0] SCS[11:0]# SMA[12:0] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] SCKE[5:0] RDCLKO RDCLKIN AGP PIPE# SBA[7:0] RBF# WBF# G_REQ# ST[2:0] G_GNT# I ISO/S I I/S I L/S H/S Z Z Z Z Z Z Z Z/I Z L Z I
Z/I Z/I Z/I Clocks
HI_STB#
BCLK Miscellaneous RSTIN# TESTIN#
I
I I
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3
Register Description
The MCH contains two sets of software accessible registers, accessed via the host processor I/O address space: * Control registers I/O mapped into the processor I/O space, which control access to PCI and AGP configuration space (see Section 3.3). * Internal configuration registers residing within the MCH are partitioned into two logical device register sets ("logical" since they reside within a single physical device). The first register set is dedicated to Host-HI Bridge functionality (i.e., DRAM configuration, other chip-set operating parameters and optional features). The second register block is dedicated to Host-AGP Bridge functions (controls AGP interface configurations and operating parameters). The MCH supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism #1 in the PCI specification. The MCH internal registers (I/O Mapped and configuration registers) are accessible by the processor. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONF_ADDR which can only be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).
3.1
Register Terminology
Term RO R/W R/W/L R/WC R/WO L Reserved Bits Description Read Only. If a register is read only, writes to this register have no effect. Read/Write. A register with this attribute can be read and written. Read/Write/Lock. A register with this attribute can be read, written, and Locked. Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. Lock. A register bit with this attribute becomes Read Only after a lock bit is set. Some of the MCH registers described in this section contain reserved bits. These bits are labeled "Reserved". Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONF_ADDR) register.
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Register Description
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Term Reserved Registers
Description In addition to reserved bits within a register, the MCH contains address locations in the configuration space that are marked "Reserved". When a "Reserved" register location is read, a random value is returned. ("Reserved" registers can be 8-, 16-, or 32-bit in size). Registers that are marked as "Reserved" must not be modified by system software. Writes to "Reserved" registers may cause system failure. Upon a Full Reset, the MCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the MCH registers accordingly.
Default Value upon a Reset
3.2
PCI Bus Configuration Space Access
The MCH and ICH2 are physically connected by the hub interface. From a configuration standpoint, the hub interface is PCI bus 0. As a result, all devices internal to the MCH and ICH2 appear to be on PCI bus 0. The system's primary PCI expansion bus is physically attached to the ICH2 and, from a configuration perspective appears to be a hierarchical PCI bus behind a PCI-toPCI bridge and, therefore, has a programmable PCI Bus number. Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration standpoint. The AGP appears to system software to be a real PCI bus behind PCI-to-PCI bridges resident as devices on PCI bus 0. The MCH contains two PCI devices within a single physical component. The configuration registers for the four devices are mapped as devices residing on PCI bus 0.
* Device 0: Host-Hub Interface Bridge/DRAM Controller. Logically this appears as a PCI device residing on PCI bus 0. Physically Device 0 contains the standard PCI registers, DRAM registers, the Graphics Aperture controller, and other MCH specific registers.
* Device 1: Host-AGP Bridge. Logically this appears as a "virtual" PCI-to-PCI bridge residing on PCI bus 0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP/PCI configuration registers (including the AGP I/O and memory address mapping). Table 6 shows the Device # assignment for the various internal MCH devices. Table 6. Intel MCH Internal Device Assignments
MCH Function DRAM Controller/8 bit HI_A Controller Host-to-AGP Bridge (virtual P2P) Bus 0, Device # Device 0 Device 1
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NOTE: A physical PCI bus 0 does not exist. The hub interface and the internal devices in the MCH and ICH2, logically constitute PCI Bus 0 to configuration software.
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3.2.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the MCH. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The MCH supports only Mechanism #1. The configuration access mechanism makes use of the CONF_ADDR Register (at I/O address 0CF8h though 0CFBh) and CONF_DATA register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONF_ADDR[31] must be 1 to enable a configuration cycle. CONF_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONF_ADDR. Any read or write to CONF_DATA results in the MCH translating the CONF_ADDR into the appropriate configuration cycle. The MCH is responsible for translating and routing the processor's I/O accesses to the CONF_ADDR and CONF_DATA registers to internal MCH configuration registers, hub interface or AGP.
3.2.2
Routing Configuration Accesses
The MCH supports two bus interfaces: the hub interface and AGP. PCI configuration cycles are selectively routed to one of these interfaces. The MCH is responsible for routing PCI configuration cycles to the proper interface. PCI configuration cycles to the ICH2 internal devices and Primary PCI (including downstream devices) are routed to the ICH2 via the hub interface. AGP configuration cycles are routed to AGP. The AGP interface is treated as a separate PCI bus from the configuration point of view. Routing of configuration AGP is controlled via the standard PCIPCI bridge mechanism using information contained within the Primary Bus Number, the Secondary Bus Number, and the Subordinate Bus Number registers of the corresponding PCI-PCI bridge device. A detailed description of the mechanism for translating processor I/O bus cycles to configuration cycles on one of the buses is described below.
PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONF_ADDR register. If the Bus Number field of CONF_ADDR is 0, the configuration cycle is targeting a PCI Bus 0 device. * The Host-HI Bridge entity in the MCH is hardwired as Device 0 on PCI Bus 0. * The Host-AGP Bridge entity in the MCH is hardwired as Device 1 on PCI Bus 0. Configuration cycles to any of the MCH's internal devices are confined to the MCH and not sent over the hub interface. Accesses to disabled MCH internal devices are forwarded over the hub interface as Type 0 Configuration Cycles.
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Register Description
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Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONF_ADDR is non-zero, and is less than the value in the Host-AGP device's Secondary Bus Number register, or greater than the value in the Host-AGP device's Subordinate Bus Number register, the MCH will generate a Type 1 hub interface configuration cycle. The ICH2 compares the non-zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI, or a downstream PCI bus.
AGP Configuration Mechanism
From the chip-set configuration perspective, AGP is seen as a PCI bus interface residing on a Secondary Bus side of the "virtual" PCI-PCI bridges referred to as the MCH Host-AGP bridge. On the Primary Bus side, the "virtual" PCI-PCI bridge is attached to PCI Bus 0. Therefore, the Primary Bus Number register is hardwired to 0. The "virtual" PCI-PCI bridge entity converts Type 1 PCI bus configuration cycles on PCI Bus 0 into Type 0 or Type 1 configuration cycles on the AGP interface. Type 1 configuration cycles on PCI Bus 0 that have a Bus Number that matches the Secondary Bus Number of the MCH's "virtual" Host-to-PCI_B/AGP bridge will be translated into Type 0 configuration cycles on the AGP interface. If the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number Register, and less than or equal to the value programmed into the Subordinate Bus Number Register, the MCH will generate a Type 1 PCI configuration cycle on AGP.
3.3
I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space: the Configuration Address (CONF_ADDR) register and the Configuration Data (CONF_DATA) register. The Configuration Address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window.
3.3.1
CONF_ADDR--Configuration Address Register
I/O Address: Default Value: Access: Size: 0CF8h Accessed as a DWord 00000000h R/W 32 bits
CONF_ADDR is a 32 bit register that can be accessed only as a DWord. A Byte or Word reference will "pass through" the Configuration Address register and the hub interface, onto the PCI bus as an I/O cycle. The CONF_ADDR register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.
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Register Description
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Bit 31 Configuration Enable (CFGE). 0 = Disable.
Descriptions
1 = Enable. Accesses to PCI configuration space are enabled. 30:24 23:16 Reserved. These bits are read only and have a value of 0. Bus Number. When Bus Number is programmed to 00h, the target of the configuration cycle is a hub interface agent (MCH, ICH2, etc.). The configuration cycle is forwarded to the hub interface, if Bus Number is programmed to 00h and the MCH is not the target (the device number is 2). If Bus Number is non-zero and matches the value programmed into the Secondary Bus Number Register of device 1, a Type 0 PCI configuration cycle will be generated on AGP. If Bus Number is non-zero, greater than the value in the Secondary Bus Number register of device 1 and less than or equal to the value programmed into the Subordinate Bus Number register of device 1 a Type 1 PCI configuration cycle will be generated on AGP. If Bus Number is non-zero, and does not fall within the ranges enumerated by device 1's Secondary Bus Number or Subordinate Bus Number register, then a hub interface Type 1 configuration cycle is generated. 15:11 Device Number. This field selects one agent on the PCI bus selected by the Bus Number field. When the Bus Number field is 00, the MCH decodes the Device Number field. The MCH is always Device Number 0 for the Host-Hub Interface bridge entity and Device Number 1 for the Host-AGP entity. Therefore, when Bus Number =0 and Device Number=0-1, the internal MCH devices are selected. If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number register a Type 0 PCI configuration cycle is generated on AGP. The MCH decodes the Device Number field ([15:11]) and assert the appropriate GAD signal as an IDSEL. For PCI-toPCI Bridge translation, one of the 16 IDSELs is generated. When bit [15] = 0, bits [14:11] are decoded to assert a signal AD[31:16] IDSEL. GAD16 is asserted to access Device 0, GAD17 for Device 1, and so forth up to Device 15 which asserts AD31. All device numbers higher than 15 cause a type 0 configuration access with no IDSEL asserted, which results in a Master Abort reported in the MCH's "virtual" PCI-PCI bridge registers. For Bus Numbers resulting in hub interface configuration cycles, the MCH propagates the device number field as A[15:11]. For bus numbers resulting in AGP type 1 configuration cycles, the device number is propagated as GAD[15:11]. 10:8 Function Number. This field is mapped to GAD[10:8] during AGP configuration cycles and A[10:8] during Hub Interface configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The MCH ignores configuration cycles to its internal devices if the function number is not equal to 0. Register Number. This field selects one register within a particular bus, device, and function as specified by the other fields in the Configuration Address register. This field is mapped to GAD[7:2] during AGP configuration cycles and A[7:2] during hub interface configuration cycles. Reserved.
7:2
1:0
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Register Description
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3.3.2
CONF_DATA--Configuration Data Register
I/O Address: Default Value: Access: Size: 0CFCh 00000000h R/W 32 bits
CONF_DATA is a 32 bit read/write window into configuration space. The portion of configuration space that is referenced by CONF_DATA is determined by the contents of CONF_ADDR.
Bit 31:0 Descriptions Configuration Data Window (CDW). If bit 31 of the CONF_ADDR register is 1, any I/O access to the CONF_DATA register will be mapped to configuration space using the contents of CONF_ADDR.
3.4
Memory-Mapped Register Space
All system memory control functions have been consolidated into a new memory-mapped address region within Device 0, Function 0. This space will be accessed using a new Base Address register (BAR) located at Device 0, Function 0 (address offset 14h). By default this BAR is invisible (i.e., read-only as 0s). Note: All accesses to these memory-mapped registers must be made as a single DWord (4 bytes) or less. Access must be aligned on a natural boundary. The high-level address map for the memory-mapped registers is shown in Table 7.
Table 7. Memory-mapped Register Address Map
Memory Address Offset 020h-02Bh 2Ch 02Dh-02Fh 030h-034h 040h-0DFh 140h-1DFh Reserved DRAM Width Register Reserved Strength Registers Reserved Reserved Register Group
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Register Description
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3.4.1
DRAMWIDTH--DRAM Width Register
Address Offset: Default Value: Access: Size: 2Ch 00h R/W 8 bits
This register determines the width of SDRAM devices populated in each row of memory.
Bit 7:6 5 Reserved. Row 5 Width. Width of devices in Row 5 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Row 4 Width. Width of devices in Row 4 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Row 3 Width. Width of devices in Row 3 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Row 2 Width. Width of devices in Row 2 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Row 1 Width. Width of devices in Row 1 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Row 0 Width. Width of devices in Row 0 0 = 16-bit wide devices, or Unpopulated (default) 1 = 8-bit wide devices Descriptions
4
3
2
1
0
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify exactly which row width field affects which clock signal.
Row Parameters 0 1 2 3 4 5
SDR Clocks Affected SCK[0], SCK[2] SCK[1], SCK[3] SCK[4], SCK[6] SCK[5], SCK[7] SCK[8], SCK[10] SCK[9], SCK[11]
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Register Description
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3.4.2
DQCMDSTR--Strength Control Register (SDQ and CMD Signal Groups)
Memory Address Offset: Default Value: Access: Size: 30h 00h R/W 8 bits
This register controls the drive strength of the I/O buffers for the DQ/DQS and CMD signal groups.
Bit 7 6:4 Reserved. CMD Strength Control (SRAS#, SCAS#, SWE#, SMA[12:0], SBS[1:0]). This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 3 2:0 Reserved. SDQ/SDQS Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X Descriptions
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Register Description
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3.4.3
CKESTR--Strength Control Register (SCKE Signal Group)
Memory Address Offset: Default Value: Access: Size: 31h 00h R/W 8 bits
This register controls the drive strength of the I/O buffers for the CKE signal group. This group has two possible loadings depending on the width of SDRAM devices used in each row of memory (x8 or x16). The proper strength can be independently programmed for each configuration. The actual strength used for each signal is determined by the DRAMWIDTH Register (offset 2Ch).
Bit 7 6:4 Reserved. SCKE x16 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 3 2:0 Reserved. SCKE x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X Descriptions
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Register Description
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3.4.4
CSBSTR--Strength Control Register (SCS# Signal Group)
Memory Address Offset: Default Value: Access: Size: 32h 00h R/W 8 bits
This register controls the drive strength of the I/O buffers for the SCS# signal group. This group has two possible loadings depending on the width of SDRAM devices used in each row of memory (x8 or x16). The proper strength can be independently programmed for each configuration. The actual strength used for each signal is determined by the DRAMWIDTH Register (offset 2Ch).
Bit 7 6:4 Reserved. SCS# x16 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 3 2:0 Reserved. SCS# x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X Descriptions
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Register Description
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3.4.5
CKSTR--Strength Control Register (Clock Signal Group)
Memory Address Offset: Default Value: Access: Size: 33h 00h R/W 8 bits
This register controls the drive strength of the I/O buffers for the Clock (CK) signal group including both the CK and CK# signals. This group has two possible loadings depending on the width of SDRAM devices used in each row of memory (x8 or x16). The proper strength can be independently programmed for each configuration. The actual strength used for each signal is determined by the DRAMWIDTH Register (offset 2Ch).
Bit 7 6:4 Reserved. CK x16 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 3 2:0 Reserved. CK x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X Descriptions
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Register Description
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3.4.6
RCVENSTR--Strength Control Register (RCVENOUT Signal Group)
Memory Address Offset: Default Value: Access: Size: 34h 00h R/W 8 bits
This register controls the drive strength of the I/O buffers for the Receive Enable Out signal group (RDCLKO# signal).
Bit 7:3 2:0 Reserved. Receive Enable Out Signal Group (RCVEnOut) Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X Descriptions
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Register Description
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3.5
Host-Hub Interface Bridge Device Registers (Device 0)
Table 8 provides the register address map for Device 0 PCI configuration space. An "s" in the Default Value column indicates that a strap determines the power-up default value for that bit.
Table 8. Intel MCH Configuration Space (Device 0)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0Dh 0Eh 0Fh 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-50h 51h 52-5Fh 60-67h 68-6Fh 70-73h 73-77h 78-7Bh 7C-7Fh 80-85h 86h Register Symbol VID DID PCICMD PCISTS RID -- SUBC BCC MLT HDR -- APBASE -- SVID SID -- CAPPTR -- AGPM -- DRB[0:7] -- DRA -- DRT DRC -- DERRSYN Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Reserved. Sub-Class Code Base Class Code Master Latency Timer Header Type Reserved. Aperture Base Configuration Reserved. Subsystem Vendor Identification Subsystem Identification Reserved. Capabilities Pointer Reserved. AGP Miscellaneous Configuration Reserved. DRAM Row Boundary (8 registers) Reserved. DRAM Row Attribute (4 registers) Reserved. DRAM Timing Register DRAM Controller Mode Reserved. DRAM Error Syndrome Default Value 8086h 1A30h 0006h 0090h 03h, 04h -- 00h 06h 00h 00h -- 00000008h -- 0000h 0000h -- A0h -- 00h -- 00h -- 00h -- 00000010h 0000h -- 00h Access RO RO RO, R/W RO, R/WC RO -- RO RO RO RO -- RO, R/W -- R/WO R/WO -- RO -- R/W -- R/W -- R/W -- R/W R/W, RO -- RO
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Register Description
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Address Offset 87-8Bh 8C-8Fh 90-96h 97h 98-9Ch 9Dh 9Eh
Register Symbol -- EAP PAM[0:6] FDHC -- SMRAM ESMRAMC Reserved.
Register Name --
Default Value
Access -- RO RO, R/W R/W -- RO, R/W, R/W/L RO, R/W, R/WC, R/W/L -- RO RO R/W -- R/W R/W -- R/W R/W R/W
Error Address Pointer Programmable Attribute Map (7 Registers) Fixed DRAM Hole Control Reserved. System Management RAM Control Extended System Mgmt RAM Control
00000000h 0000000000 0000h 00h -- 02h 38h
9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B4h B5-B7h B8-BBh BCh BDh BE-C3h C4-C5h C6-C7h C8-C9h CA-CBh CC-CDh CE-CFh D0-DDh DE-DFh E0-E3h E4-E7h E8-FFh
-- ACAPID AGPSTAT AGPCMD -- AGPCTRL APSIZE -- ATTBASE AMTT LPTT
Reserved. AGP Capability Identifier AGP Status AGP Command Reserved. AGP Control Aperture Size Reserved Aperture Translation Table Base AGP MTT Control AGP Low Priority Transaction Timer Reserved
-- 00200002h 1F000216h 00000000h -- 00000000h 00h -- 00000000h 00h 00h
TOM MCHCFG ERRSTS ERRCMD SMICMD SCICMD -- SKPD -- CAPID --
Top of Low Memory MCH Configuration Error Status Error Command SMI Command SCI Command Reserved. Scratchpad Data Reserved. Product Specific Capability Identifier Reserved.
0000h 0000h 0000h 0000h 0000h 0000h -- 0000h -- F104A009h --
R/W R/W, RO R/WC R/W R/W R/W -- R/W -- RO --
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3.5.1
VID--Vendor Identification Register (Device 0)
Address Offset: Default Value: Attribute: Size: 00-01h 8086h RO 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the DID Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0 Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
3.5.2
DID--Device Identification Register (Device 0)
Address Offset: Default Value: Attribute: Size: 02-03h 1A30h RO 16 bits
This 16-bit register combined with the VID Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0 Description Device Identification Number. This is a 16-bit value assigned to the MCH Host-Hub Interface Bridge Function #0.
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Register Description
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3.5.3
PCICMD--PCI Command Register (Device 0)
Address Offset: Default: Access: Size 04-05h 0006h R/W, RO 16 bits
Since MCH Device 0 does not physically reside on PCI0, many of the bits are not implemented.
Bit 15:10 9 Reserved. Fast Back-to-Back--RO. Not implemented; Hardwired to 0. This bit controls whether or not the master can do fast back-to-back write. Since device 0 is strictly a target this bit is not implemented. SERR Enable (SERRE)--R/W. This bit is a global enable bit for Device 0 SERR messaging. The MCH does not have an SERR# signal. The MCH communicates the SERR# condition by sending a SERR message to the ICH2. 0 =Disable. SERR message is not generated by the MCH for Device 0. 1 =Enable. The MCH is enabled to generate SERR messages over the hub interface for specific Device 0 error conditions that are individually enabled in the ERRCMD Register. The error status is reported in the ERRSTS and PCISTS registers. NOTE: This bit only controls SERR message for the Device 0. Device 1 has its own SERRE bits to control error reporting for error conditions occurring on their respective devices. 7 6 5 4 3 2 1 0 Address/Data Stepping--RO. Not implemented; Hardwired to 0. Parity Error Enable (PERRE)--RO. Not implemented; Hardwired to 0.The PERR# signal is not implemented by the MCH. VGA Palette Snoop--RO. Not implemented; Hardwired to 0. Memory Write and Invalidate Enable(MWIE)--RO. Not implemented; Hardwired to 0. Special Cycle Enable(SCE)--RO. Not implemented; Hardwired to 0. Bus Master Enable (BME)--RO. Hardwired to 1. The MCH is always enabled as a master on the hub interface. Memory Access Enable (MAE)--RO. Not implemented; Hardwired to 1. The MCH always allows access to system memory. I/O Access Enable (IOAE)--RO. Not implemented; Hardwired to 0. Descriptions
8
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Register Description
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3.5.4
PCISTS--PCI Status Register (Device 0)
Address Offset: Default Value: Access: Size: 06-07h 0090h RO, R/WC 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s on the hub interface. Since MCH Device 0 is the Host-to-hub interface bridge, many of the bits are not implemented.
Bit 15 14 Reserved. Signaled System Error (SSE)--R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = MCH Device 0 generated an SERR message over the hub interface for any enabled Device 0 error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD Registers. Device 0 error flags are read/reset from the PCISTS or ERRSTS Registers. 13 Received Master Abort Status (RMAS)--R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = MCH generated a hub interface request that receives a Master Abort completion packet or Master Abort Special Cycle. 12 Received Target Abort Status (RTAS)--R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = MCH generated a hub interface request that receives a Target Abort completion packet or Target Abort Special Cycle. 11 10:9 8 7 6:5 4 Signaled Target Abort Status (STAS)--RO. Not Implemented; Hardwired to 0. The MCH will not generate a Target Abort hub interface completion packet or special cycle. DEVSEL Timing (DEVT)--RO. Hardwired to 00. Hub interface does not comprehend DEVSEL# protocol. Master Data Parity Error Detected (DPD)--RO. Not Implemented; Hardwired to 0. PERR signaling and messaging are not implemented by the MCH. Fast Back-to-Back (FB2B)--RO. Hardwired to 1. Reserved. Capability List (CLIST)--RO. 1 = Indicates to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via the CAPPTR Register (offset 34h). CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. 3:0 Reserved. Description
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Register Description
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3.5.5
RID--Revision Identification Register (Device 0)
Address Offset: Default Value: Access: Size: 08h See table below RO 8 bits
This register contains the revision number of the MCH Device 0. These bits are read only and writes to this register have no effect.
Bit 7:0 Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the MCH Device 0. 03h = A3 Stepping 04h = B0 Stepping
3.5.6
SUBC--Sub-Class Code Register (Device 0)
Address Offset: Default Value: Access: Size: 0Ah 00h RO 8 bits
This register contains the Sub-Class Code for the MCH Device 0.
Bit 7:0 Description Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of bridge of the MCH. 00h = Host bridge.
3.5.7
BCC--Base Class Code Register (Device 0)
Address Offset: Default Value: Access: Size: 0Bh 06h RO 8 bits
This register contains the Base Class Code of the MCH Device 0.
Bit 7:0 Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH. 06h = Bridge device.
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3.5.8
MLT--Master Latency Timer Register (Device 0)
Address Offset: Default Value: Access: Size: 0Dh 00h RO 8 bits
The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this register is not implemented.
Bit 7:0 Hardwired to 00h. Writes have no effect. Description
3.5.9
HDR--Header Type Register (Device 0)
Address Offset: Default: Access: Size: 0Eh 00h RO 8 bits
This register identifies the header layout of the configuration space.
Bit 7:0 Hardwired to 00h. Writes have no effect. Description
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Register Description
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3.5.10
APBASE--Aperture Base Configuration Register (Device 0)
Offset: Default: Access: Size: 10-13h 0000_0008h R/W, RO 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or behave as hardwired to 0). To allow for flexibility (of the aperture), an additional register called APSIZE is used as a "back-end" register to control, which bits of the APBASE will behave as hardwired to 0. This register will be programmed by the MCH specific BIOS code that runs before any of the generic configuration software is run. Note: Bit 9 of the MCHCFG register is used to prevent accesses to the aperture range before this register is initialized by the configuration software and the appropriate translation table structure has been established in the system memory.
Bit 31:28 Description Upper Programmable Base Address--R/W. These bits are part of the aperture base set by configuration software to locate the base address of the graphics aperture. They correspond to bits [31:28] of the base address in the processor's address space that will cause a graphics aperture translation to be inserted into the path of any memory read or write. Default = 0000 27:22 Middle "Hardwired"/Programmable Base Address--R/W. These bits are part of the aperture base set by configuration software to locate the base address of the graphics aperture. They correspond to bits [27:4] of the base address in the processor's address space that will cause a graphics aperture translation to be inserted into the path of any memory read or write. These bits can behave as though they were hardwired to 0, if programmed to do so by the APSIZE bits of the APSIZE register. This causes configuration software to understand that the granularity of the graphics aperture base address is either finer or more coarse, depending on the bits set by MCH-specific configuration software in APSIZE. Lower "Hardwired" Base Address--RO. Hardwired to 0s. This forces a minimum aperture size selected by this register to be 4 MB. Prefetchable--RO. This bit is hardwired to 1 to identify the Graphics Aperture range as prefetchable as per the PCI Local Bus Specification for the base address registers. There are no side effects on reads, the device returns all bytes on reads, regardless of the byte enables, and the MCH may merge processor writes into this range without causing errors. 2:1 Type--RO. These bits determine addressing type and they are hardwired to "00" to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. Memory Space Indicator--RO. Hardwired to 0 to identify aperture range as a memory range.
21:4 3
0
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3.5.11
SVID--Subsystem Vendor Identification (Device 0)
Offset: Default: Access: Size: 2C-2Dh 0000h R/WO 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0 Description Subsystem Vendor ID. (Default = 0000h). This field should be programmed during boot-up. After this field is written once, it becomes read only.
3.5.12
SID--Subsystem Identification (Device 0)
Offset: Default: Access: Size: 2E-2Fh 0000h R/WO 16 bits
This value is used to identify a particular subsystem.
Bit 15:0 Description Subsystem ID. (Default = 0000h). This field should be programmed during boot-up. After this field is written once, it becomes read only.
3.5.13
CAPPTR--Capabilities Pointer (Device 0)
Offset: Default: Access: Size: 34h E4h RO 8 bits
The CAPPTR provides the offset that is the pointer to the location where the AGP standard registers are located.
Bit 7:0 Description AGP Standard Register Block Pointer Address. This address pointer indicates to software where it can find the beginning of the AGP register block. E4h = AGP register block beginning address.
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Register Description
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3.5.14
AGPM--AGP Miscellaneous Configuration Register (Device 0)
Address Offset: Default Value: Access: Size: 51h 00h R/W 8 bits
Bit 7:2 1 Reserved.
Descriptions
Aperture Access Global Enable (APEN). This bit is used to prevent access to the graphics aperture from any port (processor, hub interface, or AGP/PCI_B) before the aperture range is established by the configuration software and the appropriate translation table in system memory has been initialized. The default value is 0; thus, this field must be set after system is fully configured to enable aperture accesses.
3.5.15
DRB[0:7]--DRAM Row Boundary Registers (Device 0)
Offset: Default: Access: Size: 60-67h (DRB0-DRB7) 00h R/W 8 bits
The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM rows with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1 in DRB0 indicates that 32 MB of DRAM has been populated in the first row. Row 0 = 60h Row 1 = 61h Row 2 = 62h Row 3 = 63h Row 4 = 64h Row 5 = 65h (See Note 1) Row 6 = 66h (See Note 2) Row 7 = 67h (See Note 2) DRB0 = Total memory in row0 (in 32 MB increments) DRB1 = Total memory in row0 + row1 (in 32 MB increments) Notes: 1. DRB5 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 (in 32 MB increments) 2. DRB [7:6] must be programmed with the value contained in DBR5 Each Row is represented by a byte. Each byte has the following format.
Bit 7:0 Description DRAM Row Boundary Address. This 8 bit value defines the upper and lower addresses for each DRAM row. This 8-bit value is compared against a set of address lines to determine the upper address limit of a particular row.
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3.5.16
DRA--DRAM Row Attribute Registers (Device 0)
Offset: Default: Access: Size: 70-73h (DRA0-DRA3) 00h R/W 8 bits
The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of rows: Row 0, 1 = 70h Row 2, 3 = 71h Row 4, 5 = 72h (Used for SDRAM configuration only) Row 6, 7 = 73h (RAODD and RAEVEN fields must contain default value of 00h)
7 Rsvd 6 Row attribute for Row 1 4 3 Rsvd 2 Row Attribute for Row 0 0
7 Rsvd
6 Row attribute for Row 3
4
3 Rsvd
2 Row Attribute for Row 2
0
7 Rsvd
6 Row attribute for Row 5
4
3 Rsvd
2 Row Attribute for Row 4
0
7 Rsvd
6 Row attribute for Row 7
4
3 Rsvd
2 Row Attribute for Row 6
0
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Register Description
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Bit 7 6:4 Reserved.
Description
Row Attribute for Odd-Numbered Row (RAODD). This 3-bit field defines the page size of the corresponding row. 001 = 2 KB 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Reserved
3 2:0
Reserved. Row Attribute for Even-Numbered Row (RAEVEN). This 3-bit field defines the page size of the corresponding row. 001 = 2 KB 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Reserved
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3.5.17
DRT--DRAM Timing Register (Device 0)
Offset: Default: Access: Size: 78-7Bh 00000010h R/W 32 bits
Bit 31:19 18:16 Reserved.
Description
DRAM Idle Timer. This field determines the number of clocks the DRAM controller will remain in the idle state before it begins precharging all pages. 000 = infinite. 001 = 0 DRAM clocks 010 = 8 DRAM clocks 011 = 16 DRAM clocks 100 = 64 DRAM clocks Others = Reserved
15:11 10:9
Reserved. Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS. 00 = 7 clocks 01 = 6 clocks 10 = 5 clocks 11 = Reserved
8:6 5:4
Reserved. CAS# Latency (tCL). This bit controls the number of DRAM clocks between when a read command is sampled by the SDRAMs and when the MCH samples read data from the SDRAMs. 00 = Reserved 01 = 3 clocks 10 = 2 clocks 11 = Reserved
3 2
Reserved. DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row activate command and a read or write command to that row. 0 = 3 DRAM clocks 1 = 2 DRAM clocks
1 0
Reserved. DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row. 0 = 3 DRAM clocks 1 = 2 DRAM clocks
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Register Description
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3.5.18
DRC--DRAM Controller Mode Register (Device 0)
Offset: Default: Access: Size: 7C-7Fh 00000000h R/W, RO 32 bits
Bit 31:30
Description Revision Number (REV)--R/W. Reflects the revision number of the format used for SDRAM register definition. Currently, this field must be 00, since this revision (rev 00) is the only existing version of the specification. Initialization Complete (IC)--R/W. This bit is used for communication of software state between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Dynamic Powerdown Mode Enable--R/W. When set, the system memory controller will put a pair of rows into powerdown mode when all banks are pre-charged (closed). Once a bank is accessed, the relevant pair of rows is taken out of powerdown mode. The entry into powerdown mode is performed by de-activation of CKE. The exit is performed by activation of CKE. 0 = Disable. System memory powerdown disabled 1 = Enable. System memory powerdown enabled Note: Dynamic powerdown is a mobile only feature and not supported on desktop applications.
29
28
27:24
Active SDRAM Rows--R/W. Implementations may use this field to limit the maximum number of SDRAM rows that may be active at once. 0000 = All rows allowed to be in the active state Others = Reserved.
23:22 21:20
Reserved. DRAM Data Integrity Mode (DDIM)--R/W. These bits select the system memory data integrity mode. 00 = Non-ECC mode 10 = Error checking with correction Other = Reserved
19:11 10:8
Reserved. Refresh Mode Select (RMS)--R/W. This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = Reserved 001 = Refresh enabled. Refresh interval 15.6 us 010 = Refresh enabled. Refresh interval 7.8 us 011 = Refresh enabled. Refresh interval 64 us 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved
7
Reserved.
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Bit 6:4
Description Mode Select (SMS)--R/W. These bits select the special operational mode of the system memory interface. The special modes are intended for initialization at power up. 000 = Post Reset state. When the MCH exits reset (power-up or otherwise), the mode select field is cleared to "000". During any reset sequence, while power is applied and reset is active, the MCH asserts all CKE signals. After internal reset is deasserted, CKE signals remain deasserted until this field is written to a value different than "000". On this event, all CKE signals are asserted. During suspend, MCH internal signal triggers system memory controller to flush pending commands and enter all rows into Self-Refresh mode. As part of resume sequence, the MCH will be reset ( which will clear this bit field to "000" and maintain CKE signals deasserted). After internal reset is deasserted, CKE signals remain deasserted until this field is written to a value different than "000". On this event, all CKE signals are asserted. During entry to other low power states (C3, S1), MCH internal signal triggers DRAM controller to flush pending commands and enter all rows into Self-Refresh mode. During exit to normal mode, MCH signal triggers DRAM controller to exit Self-Refresh and resume normal operation without S/W involvement. 001 = NOP Command Enable. All processor cycles to system memory result in a NOP command on the system memory interface. 010 = All Banks Pre-charge Enable. All processor cycles to system memory result in an "all banks precharge" command on the system memory interface. 011 = Mode Register Set Enable. All processor cycles to system memory result in a "mode register" set command on the system memory interface. Host address lines are mapped to memory address lines to specify the command sent. Host address lines [15:3] are mapped to SMA[12:0]. 100 = Reserved 101 = Reserved 110 = CBR Refresh Enable. In this mode all processor cycles to system memory result in a CBR cycle on the SDRAM interface 111 = Normal operation.
3:2 1:0
Reserved. DRAM Type (DT)--RO. Used to select between supported SDRAM types. 00 = Single Data Rate (SDR) SDRAM. 01-11 = Reserved
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Register Description
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3.5.19
DERRSYN--DRAM Error Syndrome Register (Device 0)
Address Offset: Default Value: Access: Size: 86h 00h RO 8 bits
This register is used to report the ECC syndromes for each quadword of a 32 byte-aligned data quantity read from the system memory array.
Bit 7:0 Description DRAM ECC Syndrome (DECCSYN). After a system memory ECC error, hardware loads this field with a syndrome that describes the set of bits found to be in error. Note: This field is locked from the time that it is loaded up to the time when the error flag is cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple bit error will overwrite this field. In all other cases, an error that occurs after the first error and before the error flag has been cleared by software will escape recording.
3.5.20
EAP--Error Address Pointer Register (Device 0)
Address Offset: Default Value: Access: Size: 8C-8Fh 0000_0000h RO 32 bits
This register contains the address of the 32 byte-aligned data unit on which system memory ECC error(s) was detected.
Bit 31:30 29:1 Reserved. Error Address Pointer (EAP). This field is used to store address bits A[33:5] of the 32-bytealigned data unit of system memory of which an error (single bit or multi-bit error) has occurred. Note: The value of this bit field represents the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software. A multiple bit error will overwrite a single bit error. Once the error flag bits are set as a result of an error, this bit field is locked and does not change as a result of a new error until the error flag is cleared by software. 0 Reserved. Descriptions
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3.5.21
PAM[0:6]--Programmable Attribute Map Registers (Device 0)
Address Offset: Default Value: Attribute: Size: 90-96h (PAM0-PAM6) 00h R/W, RO 8 bits
The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 Kbytes to 1 Mbytes address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to host initiator only access to the PAM areas. The MCH forwards to system memory for any AGP, PCI or hub interface-initiated accesses to the PAM areas. These attributes are: RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment are claimed by the MCH and directed to system memory. Conversely, when RE = 0, the host read accesses are directed to PCI0. Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the MCH and directed to system memory. Conversely, when WE = 0, the host write accesses are directed to PCI0.
WE -
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The four bits that control each region have the same encoding and defined in the following table.
Bits [7, 3] Reserved X Bits [6, 2] Reserved X Bits [5, 1] WE 0 Bits [4, 0] RE 0 Description Disabled. System memory is disabled and all accesses are directed to the hub interface. The MCH does not respond as a PCI target for any read or write access to this area. Read Only. Reads are forwarded to system memory and writes are forwarded to the hub interface for termination. This write protects the corresponding memory segment. The MCH responds as an AGP or hub interface target for read accesses but not for any write accesses. Write Only. Writes are forwarded to system memory and reads are forwarded to the hub interface for termination. The MCH responds as an AGP or hub interface target for write accesses but not for any read accesses. Read/Write. This is the normal operating mode of system memory. Both read and write cycles from the host are claimed by the MCH and forwarded to system memory. The MCH responds as an AGP or hub interface target for both read and write accesses.
X
X
0
1
X
X
1
0
X
X
1
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Register Description
R
At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. As an example, consider BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in system memory to increase the system performance. When BIOS is shadowed in system memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. BIOS is shadowed by first performing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address, which is directed to system memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Table 9 and Figure 2 show the PAM registers and the associated attribute bits: Figure 2. PAM Register Attributes
Offset PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 7 R Reserved Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable 0=Disable 6 R 5 WE 4 RE 3 R 2 R 1 WE 0 RE Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved Reserved
pam
96h 95h 94h 93h 92h 91h 90h
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Table 9. PAM Register Attributes
PAM Reg PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] R R R R R R R R R R R R R Attribute Bits Reserved R R R R R R R R R R R R R WE WE WE WE WE WE WE WE WE WE WE WE RE RE RE RE RE RE RE RE RE RE RE RE RE 0F0000h-0FFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh BIOS Area ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset 90h 90h 91h 91h 92h 92h 93h 93h 94h 94h 95h 95h 96h 96h
For details on overall system address mapping scheme see Chapter 4.
DOS Application Area (00000h-9FFFh)
The DOS area is 640 KB in size and it is further divided into two parts. The 512 KB area at 0h to 7FFFFh is always mapped to the system memory controlled by the MCH, while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCI0 or to system memory. By default this range is mapped to system memory and can be declared as a system memory hole (accesses forwarded to PCI0) via MCH FDHC configuration register.
Video Buffer Area (A0000h-BFFFFh)
Attribute bits do not control this 128 KB area. The host -initiated cycles in this region are always forwarded to either PCI0 or AGP unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA control mechanism of the "virtual" PCI-PCI bridge device embedded within the MCH. This area can be programmed as SMM area via the SMRAM register. When used as a SMM space, this range cannot be accessed from the hub interface or AGP.
Expansion Area (C0000h-DFFFFh)
This 128 KB area is divided into eight 16 KB segments, which can be assigned with different attributes via PAM control register as defined by the table above.
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Extended System BIOS Area (E0000h-EFFFFh)
This 64 KB area is divided into four 16 KB segments that can be assigned with different attributes via PAM control register as defined by the table above.
System BIOS Area (F0000h-FFFFFh)
This area is a single 64 KB segment, which can be assigned with different attributes via PAM control register as defined by the table above.
3.5.22
FDHC--Fixed DRAM Hole Control Register (Device 0)
Address Offset: Default Value: Access: Size: 97h 00h R/W 8 bits
This 8-bit register controls a fixed DRAM hole: 15-16 MB.
Bit 7 Description Hole Enable (HEN). This bit enables a memory hole in DRAM space. Host cycles matching an enabled hole are passed on to the ICH2 through the hub interface. The hub interface cycles matching an enabled hole will be ignored by the MCH. Note that a selected hole is not remapped. 0 = Disabled. No hole 1 = 15 MB-16 MB (1 MB hole) 6:0 Reserved.
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3.5.23
SMRAM--System Management RAM Control Register (Device 0)
Address Offset: Default Value: Access: Size: 9Dh 02h R/W, RO, R/W/L 8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when the G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Bit 7 6 Reserved. SMM Space Open (D_OPEN)--R/W/L. When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only. SMM Space Closed (D_CLS)--R/W. When D_CLS = 1, SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This allows SMM software to reference "through" SMM space to update the display, even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMM space. 4 SMM Space Locked (D_LCK)--R/W. When D_LCK is set to 1, D_OPEN is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become "Read Only". D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Global SMRAM Enable (G_SMRAME)--R/W/L. 0 =Disable 1 =Enable. Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has to be set to 1. Once D_LCK is set, this bit becomes read only. 2:0 Compatible SMM Space Base Segment (C_BASE_SEG)--RO. This field indicates the location of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to the hub interface. 010 = Hardwired to 010 to indicate that the MCH supports the SMM space at A0000h-BFFFFh. Description
5
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Register Description
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3.5.24
ESMRAMC--Extended System Mgmt RAM Control Register (Device 0)
Address Offset: Default Value: Access: Size: 9Eh 38h RO, R/W, R/WC, R/W/L 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB.
Bit 7 Description H_SMRAM_EN (H_SMRAME)--R/W/L. Controls the SMM memory space location (i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory space is enabled. SMRAM accesses from FEDA_0000h to FEDB_FFFFh are remapped to DRAM address 000A0000h to 000BFFFFh. Once D_LCK is set, this bit becomes read only. 6 E_SMRAM_ERR (E_SMERR)--R/WC. 0 = The software must write a 1 to this bit to clear it. 1 = This bit is set when host accesses the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. 5 4 3 2:1 SMRAM_Cache (SM_CACHE)--RO. Hardwired to 1. SMRAM_L1_EN (SM_L1)--RO. Hardwired to 1. SMRAM_L2_EN (SM_L2)--RO. Hardwired to 1. TSEG_SZ[1-0] (T_SZ)--R/W. Selects the size of the TSEG memory block if enabled. This memory is taken from the top of system memory space (i.e., TOM - TSEG_SZ), which is no longer claimed by the memory controller (all accesses to this space are sent to the hub interface if TSEG_EN is set). This field decodes as follows: 00 = (TOM-128 KB) to TOM 01 = (TOM-256 KB) to TOM 10 = (TOM-512 KB) to TOM 11 = (TOM-1 MB) to TOM Once D_LCK is set, this bit becomes read only. 0 TSEG_EN (T_EN)--R/W/L. Enabling of SMRAM memory (TSEG, 128 KB, 256 KB, 512 KB or 1 MB of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only.
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3.5.25
ACAPID--AGP Capability Identifier Register (Device 0)
Address Offset: Default Value: Access: Size: A0-A3h 0020_0002h RO 32 bits
This register provides standard identifier for AGP capability.
Bit 31:24 23:20 Reserved. Major AGP Revision Number (MAJREV). These bits provide a major revision number of AGP specification that this version of the MCH conforms. This field is hardwired to value of "0010b" (i.e., implying Rev 2.x). Minor AGP Revision Number (MINREV). These bits provide a minor revision number of AGP specification that this version of the MCH conforms. This number is hardwired to value of "0000" (i.e., implying Rev x.0) Together with the major revision number this field identifies MCH as an AGP Revision 2.0 compliant device. 15:8 Next Capability Pointer (NCAPTR). AGP capability is the first and the last capability described via the capability pointer mechanism; therefore, these bits are hardwired to 0h to indicate the end of the capability linked list. AGP Capability ID (CAPID). This field identifies the linked list item as containing AGP registers. This field has a value of 0000_0010b assigned by the PCI SIG. Description
19:16
7:0
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3.5.26
AGPSTAT--AGP Status Register (Device 0)
Address Offset: Default Value: Access: Size: A4-A7h 1F00_0217h RO 32 bits
This register reports AGP device capability/status.
Bit 31:24 Description Request Queue (RQ). This field contains the maximum number of AGP command requests the MCH is configured to manage. 1Fh = Allows a maximum of 32 outstanding AGP command requests. 23:10 9 8:6 5 4 3 2:0 Reserved. Side Band Addressing Support (SBA). Hardwired to 1 to indicate that the MCH supports side band addressing. Reserved. Greater that 4 GB Support (4G). Hardwired to 0 to indicate that the MCH does not support addresses greater than 4. Fast Write Support (FW). Hardwired to 1 to indicate that the MCH supports Fast Writes from the host to the AGP master. Reserved. Data Rate Support (RATE). Hardwired to 111. After reset, the MCH reports its data transfer rate capability. Bit 0 identifies if AGP device supports 1x data transfer mode, bit 1 identifies if AGP device supports 2x data transfer mode, bit 2 identifies if AGP device supports 4x data transfer mode. 111 = 1x, 2x, and 4x data transfer modes are supported by the MCH Note: The selected data transfer mode applies to both AD bus and SBA bus. It also applies to Fast Writes if they are enabled.
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Register Description
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3.5.27
AGPCMD--AGP Command Register (Device 0)
Address Offset: Default Value: Access: Size: A8-ABh 0000_0000h R/W 32 bits
This register provides control of the AGP operational parameters.
Bit 31:10 9 Reserved. SideBand Address Enable (SBAEN). 0 = Disable. 1 = Enable. 8 AGP Enable (AGPEN). 0 = The MCH ignores all AGP operations, including the sync cycle. Any AGP operation received while this bit is 1 will be serviced, even if this bit is set to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode, the command will be issued. 1 = The MCH will respond to AGP operations delivered via PIPE# or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1. 7:5 4 Reserved. Fast Write Enable (FWEN). 0 = When this bit is set to 0, or when the data rate bits are set to 1x mode, the memory write transactions from the MCH to the AGP master use standard PCI protocol. 1 = MCH uses the Fast Write protocol for memory write transactions from the MCH to the AGP master. Fast Writes occur at the data transfer rate selected by the DRATE bits (2:0) in this register. 3 2:0 Reserved. Data Rate (DRATE). The settings of these bits determine the AGP data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. 001 = 1x transfer mode 010 = 2x transfer mode 100 = 4x transfer mode Configuration software updates this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register in the AGP masters' configuration space.) Note: This field applies to AD and SBA buses. It also applies to Fast Writes if they are enabled. Description
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3.5.28
AGPCTRL--AGP Control Register (Device 0)
Address Offset: Default Value: Access: Size: B0-B3h 0000_0000h R/W 32 bits
This register provides for additional control of the AGP interface.
Bit 31:8 7 Reserved. GTLB Enable (GTLBEN). This bit provides enable and flush control of the GTLB. 0 =Disable (Default). GTLB is flushed by clearing the valid bits associated with each entry. 1 =Enable. Normal operations of the Graphics Translation Lookaside Buffer. 6:1 0 Reserved. Data Rate 4x Override. 1 =The RATE[2:0] bit in the AGPSTS register will be read as a 001. This bit allows the BIOS to force 1x mode. Note that this bit must be set by the BIOS before AGP configuration. Description
68
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3.5.29
APSIZE--Aperture Size (Device 0)
Address Offset: Default Value: Access: Size: B4h 00h R/W 8 bits
This register determines the effective size of the Graphics Aperture used for a particular MCH configuration. This register can be updated by the MCH specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated, the default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications; therefore, these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software.
Bit 7:6 5:0 Reserved. Graphics Aperture Size (APSIZE). Each bit in APSIZE[5:0] operates on similarly ordered bits in APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is 0, it forces the similarly ordered bit in APBASE[27:22] to behave as "hardwired" to 0. When a particular bit of this field is set to 1, it allows corresponding bit of the APBASE[27:22] to be read/write accessible. Only the following combinations are allowed: 5 1 1 1 1 1 1 0 43210 11111 11110 11100 11000 10000 00000 00000 Aperture Size 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB Description
Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond as "hardwired" to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write.
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Register Description
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3.5.30
ATTBASE--Aperture Translation Table Base Register (Device 0)
Address Offset: Default Value: Access: Size: B8-BBh 0000_0000h R/W 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base located in the system memory. This value is used by the MCH Graphics Aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical system memory address. The ATTBASE register may be dynamically changed. Note: The address provided via ATTBASE is 4 KB aligned.
Bit 31:12
Description Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in system memory. Note: It should be modified only when the GTLB has been disabled.
11:0
Reserved.
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Register Description
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3.5.31
AMTT--AGP Interface Multi-Transaction Timer Register (Device 0)
Address Offset: Default Value: Access: Size: BCh 00h R/W 8 bits
AMTT is an 8-bit register that controls the amount of time that the MCH arbiter allows AGP master to perform multiple back-to-back transactions. The MCH AMTT mechanism is used to optimize the performance of the AGP master (using PCI protocol) that performs multiple back-toback transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). The AMTT mechanism applies to the host-AGP transactions as well and it guarantees to the processor a fair share of the AGP interface bandwidth. The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current agent (either AGP master or host bridge) after which the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables this function. The AMTT value can be programmed with 8-clock granularity. For example, if the AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66 MHz) clocks.
Bit 7:3 Description Multi-Transaction Timer Count Value (MTTC). The number programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current agent (either AGP master or MCH) after which the AGP arbiter will grant the bus to another agent. Reserved.
2:0
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Register Description
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3.5.32
LPTT--AGP Low Priority Transaction Timer Register (Device 0)
Address Offset: Default Value: Access: Size: BDh 00h R/W 8 bits
LPTT is an 8-bit register similar in function to AMTT. This register is used to control the minimum tenure on the AGP for low-priority data transactions (both reads and writes) issued using PIPE# or SB mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. After this time expires, the AGP arbiter may grant the bus to another agent if there is a pending request. The LPTT does not apply in the case of high-priority request where ownership is transferred directly to high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h, the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
Bit 7:3 Description Low Priority Transaction Timer Count Value (LPTTC). The number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. Reserved.
2:0
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3.5.33
TOM--Top of Low Memory Register (Device 0)
Address Offset: Default Value: Access: Size: C4-C5h 0100h R/W 16 bits
This register contains the maximum address below 4 GB that should be treated as a memory access. Note that this register must be set to a value of 0100h (16 MB) or greater. Usually it will sit below the areas configured for the hub interface, PCI memory, and the graphics aperture.
Bit 15:4 Description Top of Low Memory (TOM). This register contains the address that corresponds to bits 31 to 20 of the maximum system memory address that lies below 4 GB. Configuration software should set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory or the graphics aperture, whichever is smaller. Programming Example: 400h = 1 GB. An access to 4000_0000h or above will be considered above the TOM and therefore not routed to system memory. It may go to AGP, aperture, or subtractively decode to the hub interface. 3:0 Reserved.
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Register Description
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3.5.34
MCHCFG--MCH Configuration Register (Device 0)
Offset: Default: Access: Size: C6-C7h 0000h R/W, RO 16 bits
Bit 15:12 11 Reserved.
Description
System Memory Frequency Select. This bit must be programmed prior to memory initialization. 0 = Reserved 1 = System Memory frequency is set to 133 MHz
11:6 5
Reserved. MDA Present (MDAP)--R/W. This bit works with the VGA Enable bit in the BCTRL1 register (device 1) to control the routing of host-initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is not set in either device 1. If the VGA enable bit is set, then accesses to I/O address range x3BCh-x3BFh are forwarded to the hub interface. MDA resources are defined as the following: Memory: I/O: 0B0000h-0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, are forwarded to the hub interface, even if the reference includes I/O locations not listed above. Refer to the Chapter 4 for further information. 4:3 2 Reserved. In-Order Queue Depth (IOQD)-RO. This bit reflects the value sampled on HA7# on the deassertion of the CPURST#. It indicates the depth of the host bus in-order queue (i.e., level of host bus pipelining). 0 = HA7# was sampled asserted (i.e., 0); the depth of the host bus in-order queue is set to 1 (i.e., no pipelining support on the host bus). 1 = HA7# was sampled 1 (i.e., undriven on the host bus); the depth of the host bus in-order queue is configured to the maximum allowed by the host bus protocol (i.e., 12). Note that the MCH has a 12 deep IOQ. Note that HA7# is not driven by the MCH during CPURST#. If an IOQ size of 1 is desired, HA7# must be driven low during CPURST# by an external source. 1 APIC Memory Range Disable (APICDIS)--R/W. 0 = The MCH sends cycles between 0_FEC0_0000 and 0_FEC7_FFFF to the hub interface. 1 = The MCH forwards accesses to the IOAPIC regions to the appropriate interface, as specified by the memory and PCI configuration registers. 0 Reserved.
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3.5.35
ERRSTS--Error Status Register (Device 0)
Address Offset: Default Value: Access: Size: C8-C9h 0000h R/WC 16 bits
This register is used to report various error conditions via the hub interface messages to ICH2. An SERR, SMI, or SCI error message may be generated via the hub interface on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers, respectively. These bits are set, regardless of whether or not the SERR is enabled and generated.
Bit 15:10 9 Reserved. LOCK to non-DRAM Memory Flag (LCKF). 0 =Software must write a 1 to clear this status bit. 1 =Indicates that a host initiated LOCK cycle targeting non-DRAM memory space occurred. 8:7 6 Reserved. SERR on Hub Interface Target Abort (TAHLA). 0 =Software must write a 1 to clear this status bit. 1 =MCH detected that a MCH-originated hub interface cycle was terminated with a Target Abort completion packet or special cycle. 5 MCH Detects Unimplemented Hub Interface Special Cycle (HIAUSC). 0 =Software must write a 1 to clear this status bit. 1 =MCH detected an Unimplemented Special Cycle on the hub interface. 4 AGP Access Outside of Graphics Aperture Flag (OOGF). 0 =Software must write a 1 to clear this status bit. 1 =Indicates that an AGP access occurred to an address that is outside of the graphics aperture range. 3 Invalid AGP Access Flag (IAAF). 0 =Software must write a 1 to clear this status bit. 1 =Indicates that an AGP access was attempted outside of the graphics aperture and either to the 640 KB - 1 MB range or above the top of memory. 2 Invalid Graphics Aperture Translation Table Entry (ITTEF). 0 =Software must write a 1 to clear this status bit. 1 =Indicates that an invalid translation table entry was returned in response to an AGP access to the graphics aperture. 1 Multiple-bit DRAM ECC Error Flag (DMERR). 0 =After software completes the error processing, a value of 1 is written to this bit field to set the value back to 0 and unlock the error logging mechanism. 1 =A memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the address and device number that caused the error are logged in the EAP Register. Software uses bits [1:0] to detect whether the logged error address is for Single or Multiple-bit error. Description
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Register Description
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Bit 0
Description Single-bit DRAM ECC Error Flag (DSERR). 0 =Software must write a 1 to clear this bit and unlock the error logging mechanism. 1 =A memory read data transfer had a single-bit correctable error and the corrected data was sent for the access. When this bit is set, the address, channel number, and device number that caused the error are logged in the EAP Register. When this bit is set, the EAP, CN, DN, and ES fields are locked to further single bit error updates until the processor clears this bit by writing a 1.
3.5.36
ERRCMD--Error Command Register (Device 0)
Address Offset: Default Value: Access: Size: CA-CBh 0000h R/W 16 bits
This register enables various errors to generate a SERR message via the hub interface. Since the MCH does not have an SERR# signal, SERR messages are passed from the MCH to the ICH2 over the hub interface. When a bit in this register is set, a SERR message will be generated on the hub interface when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCICMD register. Note: An error can generate one and only one error message via the hub interface. It is software's responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.
Bit 15:10 9 Reserved. SERR on Non-DRAM Lock (LCKERR). 0 = Disable.
Description
1 = Enable. The MCH will generate a hub interface SERR special cycle when a processor lock cycle is detected that does not hit system memory. 8:7 6 Reserved. SERR on Target Abort on Hub Interface Exception (TAHLA_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when a MCH-originated hub interface cycle is completed with "Target Abort" completion packet or special cycle status. 5 SERR on Detecting Hub Interface Unimplemented Special Cycle (HIAUSCERR). SERR messaging for Device 0 is globally enabled in the PCICMD register. 0 = Disable. MCH does not generate an SERR message for this event. 1 = Enable. MCH generates a SERR message over the hub interface when an unimplemented Special Cycle is received on the hub interface.
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Bit 4
Description SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when an AGP access occurs to an address outside of the graphics aperture.
3
SERR on Invalid AGP Access (IAAF_SERR). 0 = Disable. 1 = Generation of the hub interface SERR message is enabled when an AGP access occurs to an address outside of the graphics aperture and either to the 640 KB - 1 MB range or above the top of memory.
2
SERR on Invalid Translation Table Entry (ITTEF_SERR). 0 = Disable. 1 = Enable. Generation of the hub interface SERR message is enabled when an invalid translation table entry was returned in response to an AGP access to the graphics aperture.
1
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR). 0 = Disable. For systems not supporting ECC, this bit must be disabled. 1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system memory controller detects a multiple-bit error.
0
SERR on Single-bit ECC Error (DSERR). 0 = Disable. For systems that do not support ECC, this bit must be disabled. 1 = Enable. Generation of the hub interface SERR message is enabled when the MCH system memory controller detects a single bit error.
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3.5.37
SMICMD--SMI Command Register (Device 0)
Address Offset: Default Value: Access: Size: CC-CDh 0000h R/W 16 bits
This register enables various errors to generate a SMI message via the hub interface. Note: An error can generate one and only one error message via the hub interface. It is software's responsibility to make sure that when an SMI error message is enabled for an error condition, SERR and SCI error messages are disabled for that same error condition.
Bit 15:2 1 Reserved. SMI on Multiple-Bit DRAM ECC Error (DMERR). 0 =Disable. For systems not supporting ECC, this bit must be disabled. 1 =Enable. Generation of the hub interface SMI message is enabled when the MCH system memory controller detects a multiple-bit error. 0 SMI on Single-bit ECC Error (DSERR). 0 =Disable. For systems that do not support ECC, this bit must be disabled. 1 =Enable. Generation of the hub interface SMI message is enabled when the MCH system memory controller detects a single bit error. Description
3.5.38
SCICMD--SCI Command Register (Device 0)
Address Offset: Default Value: Access: Size: CE-CDh 0000h R/W 16 bits
This register enables various errors to generate a SCI message via the hub interface. Note: An error can generate one and only one error message via the hub interface. It is software's responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and SMI error messages are disabled for that same error condition.
Bit 15:2 1 Reserved. SCI on Multiple-Bit DRAM ECC Error (DMERR). 0 =Disable. For systems not supporting ECC, this bit must be disabled. 1 =Enable. Generation of the hub interface SCI message is enabled when the MCH system memory controller detects a multiple-bit error. 0 SCI on Single-bit ECC Error (DSERR). 0 =Disable. For systems that do not support ECC, this bit must be disabled. 1 =Enable. Generation of the hub interface SCI message is enabled when the MCH system memory controller detects a single bit error. Description
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3.5.39
SKPD--Scratchpad Data Register (Device 0)
Address Offset: Default Value: Access: Size: DE-DFh 0000h R/W 16 bits
Bit 15:0
Description Scratchpad [15:0]. These bits are R/W storage bits that have no effect on the MCH functionality.
3.5.40
CAPID--Product Specific Capability Identifier Register (Device 0)
Address Offset: Default Value: Access: Size: E4h 0104A009h RO 32 bits
Bit 31 System Memory Capability.
Descriptions
0 = Component only supports SDR SDRAM memory; DRAM Type field is read-only. (default) 1 = Reserved 30 Mobile Power Management Capability. 0 = Component is NOT capable of all mobile power management features and is limited to desktop use only (default) 1 = Component is capable of all mobile power management features. 29:28 27:24 Reserved. CAPID Version. 0001b = First revision of the CAPID register definition. (default) 23:16 CAPID Length. 04h = Indicates a structure length of 4 bytes. (default) 15:8 Next Capability Pointer. A0h = Points to the next Capability ID in this device (ACAPID register). (default) 7:0 CAP_ID. 1001b = Identifies the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. (default)
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3.6
Bridge Registers (Device 1)
Table 10. provides the register address map for Device 0 PCI configuration space. An "s" in the Default Value column indicates that a strap determines the power-up default value for that bit.
Table 10. Intel MCH Configuration Space (Device 1)
Address Offset 00-01h 02-03h 04-05h 06-07h 08 09 0Ah 0Bh 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1E-1Fh 20-21h 22-23h 24-25h 26-27h 28-3Dh 3Eh 3Fh 40h 41-4Fh 50-57h Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 -- SUBC1 BCC1 -- MLT1 HDR1 -- PBUSN1 SBUSN1 SUBUSN1 SMLT1 IOBASE1 IOLIMIT1 SSTS1 MBASE1 MLIMIT1 PMBASE1 PMLIMIT1 -- BCTRL1 -- ERRCMD1 -- DWTC Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Limit Address Reserved Bridge Control Reserved Error Command Reserved DRAM Write Thermal Management Control Default 8086h 1A31h 0000h 00A0h 03h, 04h -- 04h 06h -- 00h 01h -- 00h 00h 00h 00h F0h 00h 02A0h FFF0h 0000h FFF0h 0000h -- 00h -- 00h -- 0000000 0h Access RO RO RO, R/W RO, R/WC RO -- RO RO -- R/W RO -- RO R/W R/W R/W R/W R/W RO, R/WC R/W R/W R/W R/W -- RO, R/W -- R/W -- R/W/L
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Register Description
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Address Offset 58-5Fh 59-FFh
Symbol DRTC --
Name DRAM Read Thermal Management Control Reserved
Default 0000000 0h --
Access R/W/L --
3.6.1
VID1--Vendor Identification Register (Device 1)
Address Offset: Default Value: Attribute: Size: 00-01h 8086h RO 16 bits
The VID1 register contains the vendor identification number. This 16-bit register combined with the DID1 Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0 Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
3.6.2
DID1--Device Identification Register (Device 1)
Address Offset: Default Value: Attribute: Size: 02-03h 1A31h RO 16 bits
This 16-bit register combined with the VID1 register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0 Description Device Identification Number. This is a 16-bit value assigned to the MCH Device 1. MCH1 Device 1 DID = 1A31h.
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3.6.3
PCICMD1--PCI-PCI Command Register (Device 1)
Address Offset: Default: Access: Size 04-05h 0000h RO, R/W 16 bits
Bit 15:10 9 8 Reserved.
Descriptions
Fast Back-to-Back (FB2B)--RO. Not Implemented; Hardwired to 0. SERR Message Enable (SERRE1)--R/W. This bit is a global enable bit for Device 1 SERR messaging. The MCH does not have an SERR# signal. The MCH communicates the SERR# condition by sending an SERR message to the ICH2. 0 = Disable. SERR message is not generated by the MCH for Device 1. 1 = Enable. MCH is enabled to generate SERR messages over the hub interface for specific Device 1 error conditions that are individually enabled in the BCTRL register. The error status is reported in the PCISTS1 register. NOTE: This bit only controls SERR messaging for the Device 1. Device 0 has its own SERRE bit to control error reporting for error conditions occurring on Device 0.
7 6 5 4 3 2 1
Address/Data Stepping (ADSTEP)--RO. Not Implemented; Hardwired to 0. Parity Error Enable (PERRE1)--RO. Not Implemented; Hardwired to 0. Reserved. Memory Write and Invalidate Enable (MWIE)--RO. Not Implemented; Hardwired to 0. Special Cycle Enable (SCE)--RO. Not Implemented; Hardwired to 0. Bus Master Enable (BME1)--R/W. This bit is not functional. It is a R/W bit for compatibility with compliance testing software. Memory Access Enable (MAE1)--R/W. 0 = Disable. All of Device 1's memory space is disabled. 1 = Enable. The Memory and Prefetchable memory address ranges defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers are enabled.
0
I/O Access Enable (IOAE1)--R/W. 0 = Disable. All of device 1's I/O space is disabled. 1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers.
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3.6.4
PCISTS1--PCI-PCI Status Register (Device 1)
Address Offset: Default Value: Access: Size: 06-07h 00A0h RO, R/WC 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the "virtual" PCI-PCI bridge embedded n the MCH. Since this device does not physically reside on PCI_A, it reports the optimum operating conditions so that it does not restrict the capability of PCI_A.
Bit 15 14 Descriptions Detected Parity Error (DPE1)--RO. Not Implemented; Hardwired to 0. Signaled System Error (SSE1)--R/WC. 0 =Software clears this bit by writing a 1 to it. 1 =MCH device 1 generated an SERR message over the hub interface for any enabled Device 1 error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and SSTS1 register. 13 12 11 10:9 8 7 6 5 4:0 Received Master Abort Status (RMAS1)--RO. Not Implemented; Hardwired to 0. Received Target Abort Status (RTAS1)--RO. Not Implemented; Hardwired to 0. Signaled Target Abort Status (STAS1)--RO. Not Implemented; Hardwired to 0. DEVSEL# Timing (DEVT1)--RO. Hardwired to 00b. Indicate that the device 1 uses the fastest possible decode. Data Parity Detected (DPD1). Not Implemented; Hardwired to 0. Fast Back-to-Back (FB2B1)--RO. Hardwired to 1. The AGP port always supports fast back to back transactions. Reserved. 66 MHz Capability (CAP66)--RO. Hardwired to 1. Indicates that the AGP port is 66 MHz capable. Reserved.
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3.6.5
RID1--Revision Identification Register (Device 1)
Address Offset: Default Value: Access: Size: 08h See RID1 table below RO 8 bits
This register contains the revision number of the MCH device 1. These bits are read only and writes to this register have no effect.
Bit 7:0 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the MCH device 1. 03h = A3 Stepping 04h = B0 Stepping
3.6.6
SUBC1--Sub-Class Code Register (Device 1)
Address Offset: Default Value: Access: Size: 0Ah 04h RO 8 bits
This register contains the Sub-Class Code for the MCH device 1.
Bit 7:0 Description Sub-Class Code (SUBC1): This is an 8-bit value that indicates the category of bridge of the MCH. 04h = Host bridge.
3.6.7
BCC1--Base Class Code Register (Device 1)
Address Offset: Default Value: Access: Size: 0Bh 06h RO 8 bits
This register contains the Base Class Code of the MCH device 1.
Bit 7:0 Description Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the MCH device 1. 06h = Bridge device.
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3.6.8
MLT1--Master Latency Timer Register (Device 1)
Address Offset: Default Value: Access: Size: 0Dh 00h R/W 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-PCI bridge configuration software from getting "confused".
Bit 7:3 2:0 Description Not applicable but supports read/write operations. (Reads return previously written data.) Reserved.
3.6.9
HDR1--Header Type Register (Device 1)
Offset: Default: Access: Size: 0Eh 01h RO 8 bits
This register identifies the header layout of the configuration space.
Bit 7:0 Descriptions This read only field always returns 01h when read. Writes have no effect.
3.6.10
PBUSN1--Primary Bus Number Register (Device 1)
Offset: Default: Access: Size: 18h 00h RO 8 bits
This register identifies that "virtual" PCI-PCI Bridge is connected to bus #0.
Bit 7:0 Bus Number. Hardwired to 0. Descriptions
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3.6.11
SBUSN1--Secondary Bus Number Register (Device 1)
Offset: Default: Access: Size: 19h 00h R/W 8 bits
This register identifies the bus number assigned to the second bus side of the "virtual" PCI-PCI bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.
Bit 7:0 Descriptions Bus Number. Programmable. Default = 00h.
3.6.12
SUBUSN1--Subordinate Bus Number Register (Device 1)
Offset: Default: Access: Size: 1Ah 00h R/W 8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.
Bit 7:0 Descriptions Bus Number. Programmable. Default = 0.
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3.6.13
SMLT1--Secondary Master Latency Timer Register (Device 1)
Address Offset: Default Value: Access: Size: 1Bh 00h R/W 8 bits
This register controls the bus tenure of the MCH on AGP. MLT is an 8-bit register that controls the amount of time the MCH, as an AGP/PCI bus master, can burst data on the AGP bus. The count value is an 8-bit quantity; however, MLT[2:0] are reserved and have a value of 0 when determining the count value. The MCH's MLT is used to guarantee to the AGP master a minimum amount of the system resources. When the MCH begins the first AGP FRAME# cycle after being granted the bus, the counter is loaded and enabled to count from the assertion of FRAME#. If the count expires while the MCH's grant is removed (due to AGP master request), the MCH will lose the use of the bus, and the AGP master agent may be granted the bus. If the MCH's bus grant is not removed, the MCH continues to own the AGP bus, regardless of the MLT expiration or idle condition. Note that the MCH always properly terminates an AGP transaction, with FRAME# negation prior to the final data transfer. The number of clocks programmed in the MLT represents the guaranteed time slice (measured in 66 MHz AGP clocks) allotted to the MCH, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. For example, if the MLT is programmed to 18h, the value is 24 AGP clocks. The default value of MLT is 00h and disables this function. When the MLT is disabled, the burst time for the MCH is unlimited (i.e., the MCH can burst forever).
Bit 7:3 2:0 Description Secondary MLT Counter Value. Default=0s (i.e., SMLT disabled) Reserved.
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3.6.14
IOBASE1--I/O Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 1Ch F0h R/W 8 bits
This register controls the hosts to AGP I/O access routing based on the following formula: IO_BASE address O_LIMIT Only upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range is aligned to a 4 KB boundary.
Bit 7:4 3:0 Description I/O Address Base. Corresponds to A[15:12] of the I/O address. (Default=F0h) Reserved.
3.6.15
IOLIMIT1--I/O Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 1Dh 00h R/W 8 bits
This register controls the hosts to AGP I/O access routing based on the following formula: IO_BASE address IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range is at the top of a 4 KB aligned address block.
Bit 7:4 3:0 Description I/O Address Limit. Corresponds to A[15:12] of the I/O address. (Default=0) Reserved. (Only 16-bit addressing supported.)
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3.6.16
SSTS1--Secondary PCI-PCI Status Register (Device 1)
Address Offset: Default Value: Access: Size: 1E-1Fh 02A0h RO, R/WC 16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., AGP side) of the "virtual" PCI-PCI bridge embedded in the MCH.
Bit 15 Detected Parity Error (DPE1)--R/WC. 0 = Software sets this bit to 0 by writing a 1 to it. 1 = MCH detected a parity error in the address or data phase of AGP bus transactions. 14 13 Reserved. Received Master Abort Status (RMAS1)--R/WC. 0 = Software sets this bit to 0 by writing a 1 to it. 1 = MCH terminated a Host-to-AGP with an unexpected master abort. 12 Received Target Abort Status (RTAS1)--R/WC. 0 = Software sets this bit to 0 by writing a 1 to it. 1 = MCH-initiated transaction on AGP is terminated with a target abort. 11 10:9 Signaled Target Abort Status (STAS1)--RO. Hardwired to a 0. The MCH does not generate target abort on AGP. DEVSEL# Timing (DEVT1)--RO. Hardwired to 01. This 2-bit field indicates the timing of the DEVSEL# signal when the MCH responds as a target on AGP. This field indicates the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle. 01 = Medium timing. 8 7 6 5 4:0 Master Data Parity Error Detected (DPD1)--RO. Hardwired to 0. MCH does not implement G_PERR# signal. Fast Back-to-Back (FB2B1)--RO. Hardwired to 1. MCH as a target supports fast back-to-back transactions on AGP. Reserved. 66 MHz Capable (CAP66)--RO. Hardwired to 1. AGP bus is capable of 66 MHz operation. Reserved. Descriptions
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3.6.17
MBASE1--Memory Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 20-21h FFF0h R/W 16 bits
This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula: MEMORY_BASE1 address MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary.
Bit 15:4 3:0 Description Memory Address Base 1 (MEM_BASE1). Corresponds to A[31:20] of the memory address. Reserved.
3.6.18
MLIMIT1--Memory Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 22-23h 0000h R/W 16 bits
This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula: MEMORY_BASE1 address MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB aligned memory block.
Bit 15:4 3:0 Description Memory Address Limit 1(MEM_LIMIT1). Corresponds to A[31:20] of the memory address. Default=0 Reserved.
Note: Memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable AGP address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE 1and PMLIMIT1 Registers are used to map prefetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attributes to be performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP memory access performance.
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3.6.19
PMBASE1--Prefetchable Memory Base Address Register (Device 1)
Address Offset: Default Value: Access: Size: 24-25h FFF0h R/W 16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE1 address PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary.
Bit 15:4 3:0 Description Prefetchable Memory Address Base 1(PMEM_BASE1). Corresponds to A[31:20] of the memory address. Reserved.
3.6.20
PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1)
Address Offset: Default Value: Access: Size: 26-27h 0000h R/W 16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE1 address PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB aligned memory block.
Bit 15:4 3:0 Description Prefetchable Memory Address Limit 1(PMEM_LIMIT1). Corresponds to A[31:20] of the memory address. (Default=00h) Reserved.
Note: Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective.
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3.6.21
BCTRL1--PCI-PCI Bridge Control Register (Device 1)
Address Offset: Default: Access: Size 3Eh 00h RO, R/W 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. BCTRL1 provides additional control for the secondary interface (i.e., AGP) as well as some bits that affect the overall behavior of the "virtual" PCI-PCI bridge embedded in the MCH (e.g., VGA compatible address ranges mapping).
Bit 7 Descriptions Fast Back to Back Enable (FB2BEN)--RO. Hardwired to 0. Since there is only one target allowed on AGP, this bit is meaningless. The MCH will not generate FB2B cycles in 1x mode, but will generate FB2B cycles in 2x and 4x Fast Write modes. Secondary Bus Reset (SRESET)--RO. Hardwired to 0. MCH does not support generation of reset via this bit on the AGP. Note: The only way to perform a hard reset of the AGP is via the system reset either initiated by software or hardware via the ICH2. 5 Master Abort Mode (MAMODE)--RO. Hardwired to 0. This means that when acting as a master on AGP and a Master Abort occurs, the MCH will discard data on writes and return all 1s during reads. Reserved. VGA Enable (VGA_EN1)--R/W. This bit controls the routing of host-initiated transactions targeting VGA compatible I/O and memory address ranges. 0 =VGA compatible memory and I/O range accesses are not forwarded to AGP (Default). Rather, they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range registers defined above (IOBASE1, IOLIMIT1, MBASE1, MLIMIT1, PMBASE1, PMLIMIT1) 1 =MCH forwards the following host accesses to the AGP:
6
4 3
* Memory accesses in the range 0A0000h to 0BFFFFh * I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases - A[15:10] are not decoded)
When this bit is set, forwarding of these accesses issued by the host is independent of the I/O address and memory address ranges defined by the previously defined base and limit registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of this register if this bit is 1. Refer to Chapter 4 for further information. 2 ISA Enable (ISA_EN)--R/W. Modifies the response by the MCH to an I/O access issued by the host that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. 0 =Disable. All addresses defined by the IOBASE and IOLIMIT Registers for host I/O transactions are mapped to AGP (Default). 1 =Enable. MCH does not forward to AGP any I/O transactions addressing the last 768 bytes in each 1 KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to AGP, these cycles are forwarded to PCI0 where they can be subtractively or positively claimed by the ISA bridge. 1 Reserved.
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Bit 0
Descriptions Parity Error Response Enable (PER_EN)--R/W. Controls MCH's response to data phase parity errors on AGP. 0 =Address and data parity errors on AGP are not reported via the MCH hub interface SERR# messaging mechanism. Other types of error conditions can still be signaled via SERR# messaging independent of this bit's state. 1 =The G_PERR# signal is not implemented by the MCH. However, when this bit is set to 1, address and data parity errors detected on AGP are reported via hub interface SERR# messaging mechanism, if further enabled by SERRE1.
3.6.22
ERRCMD1--Error Command Register (Device 1)
Address Offset: Default Value: Access: Size: 40h 00h R/W 8 bits
Bit 7:1 0 Reserved.
Description
SERR on Receiving Target Abort (SERTA). 0 = MCH does not assert an SERR message upon receipt of a target abort on AGP. SERR messaging for Device 1 is globally enabled in the PCICMD1 register. 1 = MCH generates an SERR message over the hub interface when a target abort is received on AGP.
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3.6.23
DWTC--DRAM Write Thermal Management Control Register (Device 1)
Address Offset: Default Value: Access: Size: 50-57h 00h R/W/L 64 bits
Bit 63:41 40:28 Reserved.
Descriptions
Global Write Hexword Threshold (GWHT). The 13-bit value in this field is multiplied by 215 to arrive at the number of hexwords that must be written within the Global DRAM Write Sampling Window to cause the thermal management mechanism to be invoked. Write Thermal Management Time (WTMT). This value provides a multiplier between 0 and 63 that specifies how long thermal management remains in effect as a number of Global DRAM Write Sampling Windows. For example, if GDWSW is programmed to 1000_0000b and WTT is set to 01_0000b, then thermal management will be performed for 8192*105 host clocks (@ 100 MHz) seconds once invoked (128 * 4*105 host clocks * 16).
27:22
21:15
Write Thermal Management Monitoring Window (WTMMW). The value in this register is padded with four 0s to specify a window of 0-2047 host clocks with a 16-clock granularity. While the thermal management mechanism is invoked, system memory writes are monitored during this window. If the number of hexwords written during the window reaches the Write Thermal Management Hexword Maximum (bits 14:3), then write requests are blocked for the remainder of the window. Write Thermal Management Hexword Maximum (WTMHM). The Write Thermal Management Hexword Maximum defines the maximum number of hexwords between 0-4095 that are permitted to be written to system memory within one Write Thermal Management Monitoring Window. Write Thermal Management Mode (WTMMode). 00 = Thermal management via Counters and Hardware Thermal Management_on signal mechanisms disabled. 01 = Hardware Thermal Management_on signal mechanism is enabled. In this mode, as long as the Thermal Management_on signal is asserted, write thermal management is in effect based on the settings in WTMW and WTHM. When the Thermal Management_on signal is deasserted, write thermal management stops and the counters associated with the WTMW and WTHM are reset. When the hardware Thermal Management_on signal mechanism is not enabled, the Thermal Management_on signal has no effects. 10 = Counter mechanism controlled through GDWSW and GWHT is enabled. When the threshold set in GDWSW and GWHT is reached, thermal management start/stop cycles occur based on the settings in WTT, WTMW and WTHM. 11 = Reserved.
14:3
2:1
0
START Write Thermal Management (SWTM). Software writes to this bit to start and stop write thermal management. 0 = Write thermal management stops and the counters associated with WTMW and WTHM are reset. 1 = Write thermal management begins based on the settings in WTMW and WTHM, and remains in effect until this bit is reset to 0.
0
Reserved.
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3.6.24
DRTC--DRAM Read Thermal Management Control Register (Device 1)
Address Offset: Default Value: Access: Size: 58-5Fh 0000_0000_0000_0000h R/W/L 64 bits
Bit 63:41 40:28 Reserved.
Descriptions
Global Read Hexword Threshold (GRHT). The thirteen-bit value held in this field is multiplied by 215 to arrive at the number of hexwords that must be written within the Global DRAM Read Sampling Window to cause the thermal management mechanism to be invoked. Read Thermal Management Time (RTMT). This value provides a multiplier between 0 and 63 that specifies how long counter-based read thermal management remains in effect as a number of Global DRAM Read Sampling Windows. For example, if GDRSW is programmed to 1000_0000b and RTT is set to 01_0000b, then read thermal management will be performed for 8192*105 host clocks (@ 100 MHz) seconds once invoked (128 * 4*105 host clocks * 16). Read Thermal Management Monitoring Window (RTMMW). The value in this register is padded with four 0s to specify a window of 0-2047 host clocks with 16-clock granularity. While the thermal management mechanism is invoked, system memory reads are monitored during this window. If the number of hexwords read during the window reaches the Read Thermal Management Hexword Maximum (bits 14:3), then read requests are blocked for the remainder of the window. Read Thermal Management Hexword Maximum (RTMHM). This field defines the maximum number of hexwords between 0-4095 that are permitted to be read from system memory within one Read Thermal Management Monitoring Window. Read Thermal Management Mode (RTMMode). 00 = Thermal management via counters and Hardware Thermal Management_on signal mechanisms disabled. 01 = Hardware Thermal Management_on signal mechanism is enabled. In this mode, as long as the Thermal Management_on signal is asserted, read thermal management is in effect based on the settings in RTMW and RTHM. When the Thermal Management_on signal is deasserted, read thermal management stops and the counters associated with the RTMW and RTHM are reset. When the hardware Thermal Management_on signal mechanism is not enabled, the Thermal Management_on signal has no effects. 10 = Counter mechanism controlled through GDRSW and GRHT is enabled. When the threshold set in GDRSW and GRHT is reached, thermal management start/stop cycles occur based on the settings in RTT, RTMW and RTHM. 11 = Reserved.
27:22
21:15
14:3
2:1
0
START Read Thermal Management (SRTM). Software writes to this bit to start and stop read thermal management. 0 = Read thermal management stops and the counters associated with RTMW and RTHM are reset. 1 = Read thermal management begins based on the settings in RTMW and RTHM, and remains to be in effect until this bit is reset to 0.
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System Address Map
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System Address Map
A system based on the 845 chipset supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O regions are used solely to control the operation of devices in the system. When the MCH receives a write request whose address targets an invalid space, the data is ignored. For reads, the MCH responds by returning all zeros on the requesting interface.
4.1
Memory Address Ranges
The system memory map is broken into two categories: * Extended Memory Range (1 MB to 4 GB). The second is extended memory, existing between 1MB and 4GB. It contains a 32-bit memory space, which is used for mapping PCI, AGP, APIC, SMRAM, and BIOS memory spaces. * DOS Compatible Area (below 1 MB). The final range is a DOS legacy space, which is used for BIOS and legacy devices on the LPC interface.
Figure 3. Addressable Memory Space
16 GB Additional System M em ory Address Range 4 GB PCI Mem ory Address Range Top of Low Mem ory System M em ory Address Range 1 MB DOS Legacy Address Range Independently Program m able Non-overlapping W indows Hub Interface AG P Graphics Aperture I/O Aperture APICs
sys_addr_map_1
These address ranges are always mapped to system memory, regardless of the system configuration. Memory may be taken out of the system memory segment for use by System Management Mode (SMM) hardware and software. The Top of Low Memory (TOM) register defines the top of system memory. Note that the address of the highest 16 MB quantity of valid memory in the system is placed into the GBA15 register. For memory populations <3 GB, this value will be the same as the one programmed into the TOM register. For other memory configurations, the two are unlikely to be the same, since the PCI configuration portion of the BIOS software will program the TOM register to the maximum value that is less than the amount of memory in the system and that allows enough room for all populated PCI devices.
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Figure 4. DOS Compatible Area Address Map
Upper, Lower, Expansion Card BIOS and Buffer Area 0C0000h 0B8000h Standard PCI/ISA Video Mem ory (SMM Mem ory) 0B0000h 0A0000h Monochrom e Display Adapter Space 1 MB Controlled by PAM[6:0] 768 KB 736 KB 704 KB 640 KB Controlled by VGA Enable and MDA Enable
= Optional AGP = Optional System Mem ory = System Mem ory
sys_addr_map_2
Figure 5. Extended Memory Range Address Map
1_0000_0000 (4 G B) High BIO S, Optional extended SM RAM FF00_0000 Hub Interface (always) FEF0_0000 Local APIC Space FEE0_0000 Hub Interface (always) FED0_0000 I/O APIC Space FEC8_0000 I/O APIC Space FEC0_0000 AGP/PCI T op of Low Mem ory (TOM) Extended SMRAM Space T EM - TSEG
100C_0000 Extended SMRAM (translated to < 1 M B) 100A_0000
0100_0000 (16 MB) ISA Hole 00F0_0000 (15 MB) = 0010_0000 (1 MB)
sys_addr_map_3
=
System Mem ory Region
Optional System Mem ory Region
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4.1.1
VGA and MDA Memory Space
Video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. The address ranges in this memory space are: * VGAA * MDA * VGAB 0_000A_0000 to 0_000A_FFFF 0_000B_0000 to 0_000B_7FFF 0_000B_8000 to 0_000B_FFFF
By default, accesses to these ranges are forwarded to the hub interface. However, if the VGA_EN1 bit is set in the BCTRL1 configuration register, transactions within the VGA and MDA spaces are sent to AGP. If the MCHCFG.MDAP configuration bit is set, accesses that fall within the MDA range are sent to the hub interface independent of the setting of the VGA_EN1 bit. If the MCHCFG.MDAP configuration bit is set, accesses in the MDA range are sent to the hub interface, independent of the setting of the VGA_EN1 bit. Legacy support requires the ability to have a second graphics controller (monochrome) in the system. In an 845 chipset system, accesses in the standard VGA range are forwarded to AGP. Since the monochrome adapter may be on the hub interface or (or ISA) bus, the MCH must decode cycles in the MDA range and forward them to the hub interface. This capability is controlled by a configuration bit (MCHCFG.MDAP). In addition to the memory range B0000h to B7FFFh, the MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh and forwards them to the hub interface. An optimization allows the system to reclaim the memory displaced by these regions. If SMM memory space is enabled by SMRAM.G_SMRARE and either the SMRAM.D_OPEN bit is set or the system bus receives an SMM-encoded request for code (not data), then the transaction is steered to system memory rather than the hub interface. Under these conditions, the VGA_EN1 bit and the MDAP bit are ignored.
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4.1.2
PAM Memory Spaces
The address ranges in this memory space are: * PAMC0 * PAMC4 * PAMC8 * PAMCC * PAMD0 * PAMD4 * PAMD8 * PAMDC * PAME0 * PAME4 * PAME8 * PAMEC * PAMF0 0_000C_0000 to 0_000C_3FFF 0_000C_4000 to 0_000C_7FFF 0_000C_8000 to _000C_BFFF 0_000C_C000 to 0_000C_FFFF 0_000D_0000 to 0_000D_3FFF 0_000D_4000 to 0_000D_7FFF 0_000D_8000 to 0_000D_BFFF 0_000D_C000 to 0_000D_FFFF 0_000E_0000 to 0_000E_3FFF 0_000E_4000 to 0_000E_7FFF 0_000E_8000 to 0_000E_BFFF 0_000E_C000 to 0_000E_FFFF 0_000F_0000 to 0_000F_FFFF
The 256 KB PAM region is divided into three parts: * ISA expansion region; 128 KB area between 0_000C_0000h-0_000D_FFFFh * Extended BIOS region; 64 KB area between 0_000E_0000h-0_000E_FFFFh * System BIOS region; 64 KB area between 0_000F_0000h-0_000F_FFFFh. The ISA expansion region is divided into eight 16 KB segments. Each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled. Typically, these blocks are mapped through MCH and are subtractively decoded to ISA space. The extended system BIOS region is divided into four 16 KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main system memory or to the hub interface. Typically, this area is used for RAM or ROM. The system BIOS region is a single 64 KB segment. This segment can be assigned read and write attributes. It is by default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating the read/write attributes, the MCH can "shadow" BIOS into system memory.
4.1.3
ISA Hole Memory Space
BIOS software may optionally open a "window" between 15 MB and 16 MB (0_00F0_0000h to 0_00FF_FFFFh) that relays transactions to the hub interface instead of completing them with a system memory access. This window is opened by programming the FDHC.HEN configuration field.
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4.1.4
TSEG SMM Memory Space
The TSEG SMM space (TOM - TSEG to TOM) allows system management software to partition a region of system memory just below the top of low memory (TOM) that is accessible only by system management software. This region may be 128 KB, 256 KB, 512 KB, or 1 MB in size, depending on the ESMRAMC.TSEG_SZ field. SMM memory is globally enabled by SMRAM.G_SMRAME. Requests can access SMM system memory when either SMM space is open (SMRAM.D_OPEN) or the MCH receives an SMM code request on its system bus. To access the TSEG SMM space, TSEG must be enabled by ESMRAMC.T_EN. When all of these conditions are met, then a system bus access to the TSEG space (between TOM-TSEG and TOM) is sent to system memory. If the high SMRAM is not enabled or if the TSEG is not enabled, then all memory requests from all interfaces are forwarded to system memory. If the TSEG SMM space is enabled, and an agent attempts a non-SMM access to TSEG space, then the transaction is specially terminated. Note: Hub interface and AGP originated accesses are not allowed to SMM space.
4.1.5
IOAPIC Memory Space
The IOAPIC space (0_FEC0_0000h to 0_FEC7_FFFFh) is used to communicate with IOAPIC interrupt controllers that may be populated on the hub interface. Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor accesses to the IOAPIC0 region are always sent to the hub interface.
4.1.6
System Bus Interrupt APIC Memory Space
The system bus interrupt space (0_FEE0_0000h to 0_FEEF_FFFFh) is the address used to deliver interrupts to the system bus. Any device on AGP may issue a memory write to 0FEEx_xxxxh. The MCH forwards this memory write, along with the data, to the system bus as an Interrupt Message Transaction. The MCH terminates the system bus transaction by providing the response and asserting TRDY#. This memory write cycle does not go to system memory.
4.1.7
High SMM Memory Space
The HIGHSMM space (0_FEDA_0000h to 0_FEDB_FFFFh) allows cacheable access to the compatible SMM space by re-mapping valid SMM accesses between 0_FEDA_0000 and 0_FEDB_FFFF to accesses between 0_000A_0000 and 0_000B_FFFF. The accesses are remapped when SMRAM space is enabled; an appropriate access is detected on the system bus, and when ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory accesses from any hub interface or AGP are specially terminated: reads are provided with the value from address 0 while writes are ignored entirely.
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4.1.8
AGP Aperture Space (Device 0 BAR)
Processors and AGP devices communicate through a special buffer called the "graphics aperture" (APBASE to APBASE + APSIZE). This aperture acts as a window into main system memory and is defined by the APBASE and APSIZE configuration registers of the MCH. Note that the AGP aperture must be above the top of memory and must not intersect with any other address space.
4.1.9
AGP Memory and Prefetchable Memory
Plug-and-play software configures the AGP memory window to provide enough memory space for the devices behind this PCI-to-PCI bridge. Accesses whose addresses fall within this window are decoded and forwarded to AGP for completion. The address ranges are: * M1 * PM1 MBASE1 to MLIMIT1 PMBASE1 to PMLIMIT1
Note that these registers must be programmed with values that place the AGP memory space window between the value in the TOM register and 4 GB. In addition, neither region should overlap with any other fixed or relocatable area of memory.
4.1.10
Hub Interface Subtractive Decode
All accesses that fall between the value programmed into the TOM register and 4 GB (i.e., TOM to 4 GB) are subtractively decoded and forwarded to the hub interface if they do not decode to a space that corresponds to another device.
4.2
AGP Memory Address Ranges
The MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in MCH device 1 configuration space. The first range is controlled via the Memory Base Address (MBASE1) register and Memory Limit Address (MLIMIT1) register. The second range is controlled via the Prefetchable Memory Base Address (PMBASE1) register and Prefetchable Memory Limit Address (PMLIMIT1) register The MCH positively decodes memory accesses to AGP memory address space as defined by the following equations: * Memory_Base_Address Address Memory_Limit_Address * Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address The plug-and-play configuration software programs the effective size of the range and it depends on the size of memory claimed by the AGP device. Note: The MCH device 1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP bus that require such a window.
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4.2.1
AGP DRAM Graphics Aperture
Memory-mapped, graphics data structures can reside in a Graphics Aperture to system memory. This aperture is an address range defined by the APBASE and APSIZE registers of the MCH device 0. The APBASE register follows the standard base address register template as defined by the PCI Local Bus Specification, Revision 2.1. The size of the range claimed by the APBASE is programmed via "back-end" register APSIZE (programmed by the chipset specific BIOS before plug-and-play session is performed). APSIZE allows the BIOS software to pre-configure the aperture size to be 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB or 256 MB. By programming APSIZE to a specific size, the corresponding lower bits of APBASE are forced to 0 (behave as hardwired). The default value of APSIZE forces an aperture size of 256 MB. The aperture address range is naturally aligned. Accesses within the aperture range are forwarded to the system memory subsystem. The MCH translates the originally issued addresses via a translation table maintained in system memory. The aperture range should be programmed as non-cacheable in the processor caches. Note: Plug-and-play software configuration model does not allow overlap of different address ranges. Therefore the AGP Graphics Aperture and AGP memory address range are independent address ranges that may abut, but cannot overlap one another.
4.3
System Management Mode (SMM) Memory Range
The MCH supports the use of system memory as System Management RAM (SMRAM) enabling the use of System Management Mode. The MCH supports three SMRAM options: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM (SMRAM) space provides a memory area that is available for the SMI handler's and code and data storage. This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM. The MCH provides three SMRAM options: * Below 1 MB option that supports compatible SMI handlers. * Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM. * Optional larger write-back cacheable T_SEG area from 128 KB to 1 MB in size above 1 MB that is reserved from the highest area in system memory. The above 1 MB solutions require changes to compatible SMRAM handlers' code to properly execute above 1 MB. Note: Masters from the hub interface and AGP are not allowed to access the SMM space.
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4.3.1
SMM Space Definition
Its addressed SMM space and its DRAM SMM space define SMM space. The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space. System memory SMM space is defined as the range of physical system memory locations containing the SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped and, therefore, the addressed and DRAM SMM space is the same address range. Since the High SMM space is remapped the addressed and system memory SMM space is a different address range. Note that the High system memory space is the same as the Compatible Transaction Address space. Therefore, the table below describes three unique address ranges: * Compatible Transaction Address * High Transaction Address * TSEG Transaction Address
Table 11. SMM Space Address Ranges
SMM Space Enabled Compatible High TSEG Transaction Address Space A0000h to BFFFFh 0FEDA0000h to 0FEDBFFFFh (TOM-TSEG_SZ) to TOM System Memory Space A0000h to BFFFFh A0000h to BFFFFh (TOM-TSEG_SZ) to TOM
Note: High SMM: This is different than in some previous chipsets where the High segment was the 384 KB region from A0000h to FFFFFh. Note: TSEG SMM: Note that this is different than in previous chipsets where the TSEG address space was offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just under the TOM. In the MCH the 256 MB does not offset the TSEG region and it is not remapped.
4.3.2
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and may cause the system to hang: * The Compatible SMM space must not be setup as cacheable. * High or TSEG SMM transaction address space must not overlap address space assigned to system memory, the AGP aperture range, or to any "PCI" devices (including hub interface and AGP devices). This is a BIOS responsibility. * Both D_OPEN and D_CLOSE must not be set to 1 at the same time. * When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available system memory. This is a BIOS responsibility. * Any address translated through the AGP Aperture GTLB must not target system memory from 000A0000h to 000FFFFFh.
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4.4
I/O Address Space
The MCH does not support the existence of any other I/O devices beside itself on the system bus. The MCH generates either hub interface or AGP bus cycles for all processor I/O accesses. The MCH contains two internal registers in the processor I/O space: Configuration Address (CONF_ADDR) register and Configuration Data (CONF_DATA) register. These locations are used to implement the PCI configuration space access mechanism and as described in Chapter 3. The processor allows 64 KB+3 bytes to be addressed within the I/O space. The MCH propagates the processor I/O address without any translation on to the destination bus and therefore provides addressability for 64 KB+3 byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-around when signal A16# address signal is asserted. A16# is asserted on the system bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh. The I/O accesses (other than ones used for configuration space access) are forwarded normally to the hub interface unless they fall within the AGP I/O address range as defined by the mechanisms explained below. The MCH does not post I/O write cycles to IDE. The MCH never responds to I/O or configuration cycles initiated on AGP or the hub interface. Hub interface transactions requiring completion are terminated with "master abort" completion packets on the hub interface. Hub interface write transactions not requiring completion are dropped. AGP/PCI I/O reads are never acknowledged by the MCH.
4.5
Intel(R) MCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three interfaces (i.e., processor system bus, hub interface, or AGP).
4.5.1
Hub Interface Decode Rules
The MCH accepts accesses from the hub interface with the following address ranges: * All memory read and write accesses to main DRAM (except SMM space). * All memory write accesses from the hub interface to AGP memory range defined by MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1. * All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE. * Memory writes to VGA range on AGP if enabled. All memory reads from the hub interface that target >4 GB memory range are terminated with a master abort completion, and all memory writes (>4 GB) from the hub interface are ignored.
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4.5.2
AGP Interface Decode Rules
Cycles Initiated Using AGP FRAME# Protocol
The MCH does not support any AGP FRAME# access targeting the hub interface. The MCH claims AGP-initiated memory read and write transactions decoded to the system memory range or the Graphics Aperture range. All other memory read and write requests will be master-aborted by the AGP initiator as a consequence of MCH not responding to a transaction. Under certain conditions, the MCH restricts access to the DOS Compatibility ranges governed by the PAM registers by distinguishing access type and destination bus. The MCH does NOT accept AGP FRAME# write transactions to the compatibility ranges if the PAM designates system memory as writeable. If accesses to a range are not write-enabled by the PAM, the MCH does not respond and the cycle results in a master-abort. The MCH accepts AGP FRAME# read transactions to the compatibility ranges if the PAM designates system memory as readable. If accesses to a range are not read-enabled by the PAM, the MCH does not respond and the cycle results in a master-abort. If agent on AGP issues an I/O, PCI Configuration or PCI Special Cycle transaction, the MCH does not respond and cycle results in a master-abort.
Cycles Initiated Using AGP PIPE# or SB Protocol
All cycles must reference system memory; that is, system memory address range (including PAM) or Graphics Aperture range (also physically mapped within system memory but using different address range). AGP accesses to SMM space are not allowed. AGP-initiated cycles that target system memory are not snooped on the host bus, even if they fall outside of the AGP aperture range. If a cycle is outside of the system memory range, then it terminates as follows: * Reads remap to memory address 0h, return data from address 0h, and set the IAAF error bit in ERRSTS register in device 0 * Writes are terminated internally without affecting any chip signals or system memory
AGP Accesses to MCH that Cross Device Boundaries
For AGP FRAME# accesses, when an AGP master gets disconnected, it resumes at the new address which allows the cycle to be routed to or claimed by the new target. Therefore, the target on potential device boundaries should disconnect accesses. The MCH disconnects AGP FRAME# transactions on 4 KB boundaries. AGP PIPE# and SBA accesses are limited to 256 bytes and must hit system memory. Read accesses crossing a device boundary will return invalid data when the access crosses out of system memory. Write accesses crossing out of system memory will be discarded. The IAAF Error bit will be set.
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5
Functional Description
This chapter describes the system bus that connects the MCH to the processor, the system memory interface, the AGP interface, the MCH power and thermal management, the MCH clocking, and the MCH system reset and power sequencing.
5.1
System Bus
The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. Source synchronous transfers are used for the address and data signals. The address signals are double pumped and a new address can be generated every other bus clock. At 100 MHz bus frequency, the address signals run at 200 MT/s for a maximum address queue rate of 50 M addresses/sec. The data is quad pumped and an entire 64-byte cache line can be transferred in two bus clocks. At 100 MHz bus frequency, the data signals run at 400 MT/s for a maximum bandwidth of 3.2 GB/s. The MCH supports a 12 deep IOQ. The MCH supports two outstanding deferred transactions on the system bus. The two transactions must target different I/O interfaces as only one deferred transaction can be outstanding to any single I/O interface at a time.
5.1.1
Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from the system bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the power consumption of the MCH. DBI[3:0]# indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
DBI[3:0]# DBI0# DBI1# DBI2# DBI3# Data Bits HD[15:0]# HD[31:16]# HD[47:32]# HD[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding DBI# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or the MCH receives data, it monitors DBI[3:0]# to determine if the corresponding data segment should be inverted.
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5.1.2
System Bus Interrupt Delivery
The Pentium 4 processor supports the system bus interrupt delivery; the APIC serial bus interrupt delivery mechanism is not supported. Interrupt-related messages are encoded on the system bus as "Interrupt Message Transactions". In an 845 chipset platform, system bus interrupts can originate from the processor on the system bus, or from a downstream device on the hub interface or AGP. In the later case the MCH drives the "Interrupt Message Transaction" onto the system bus. In an 845 chipset platform, the ICH2 contains IOxAPICs, and its interrupts are generated as upstream hub interface memory writes. Furthermore, PCI 2.2 defines MSIs (Message Signaled Interrupts) that are also in the form of memory writes. A PCI 2.2 device can generate an interrupt as an MSI cycle on it's PCI bus, instead of asserting a hardware signal to the IOxAPIC. The MSI can be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface memory write. Alternatively, the MSI can be directed directly to the system bus. The target of a MSI is dependent on the address of the interrupt memory write. The MCH forwards inbound hub interface and AGP (PCI semantic only) memory writes to address 0FEEx_xxxxh, to the system bus as "Interrupt Message Transactions".
5.1.3
Upstream Interrupt Messages
The MCH accepts message-based interrupts from AGP (PCI semantics only) or its hub interface and forwards them to the system bus as Interrupt Message Transactions. The interrupt messages presented to the MCH are in the form of memory writes to address 0FEEx_xxxxh. At the hub interface or AGP interface, the memory write interrupt message is treated like any other memory write; it is either posted to the inbound data buffer (if space is available) or retried (if data buffer space is not immediately available). Once posted, the memory write from AGP or the hub interface to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the MCH to the system bus as an Interrupt Message Transaction.
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5.2
System Memory Interface
The 845 chipset can be configured to support PC133 SDRAM.
5.2.1
Single Data Rate (SDR) SDRAM Interface Overview
The MCH integrates a system memory SDRAM controller with a 64-bit wide interface and twelve system memory clock signals (each at 133 MHz). The MCH's system memory buffers support LVTTL (SDRAM) signaling at 133 MHz. The MCH includes support for: * Up to 3 GB of 133 MHz SDR SDRAM * PC133 unbuffered 168 pin SDR SDRAM DIMMs * Maximum of 3 DIMMs, single-sided and/or double-sided * Configurable optional ECC The two bank-select lines SBS[1:0] and the thirteen address lines (SMA[12:0]) allow the MCH to support 64-bit wide DIMMs using 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technologies. While address lines SMA[9:0] determine the starting address for a burst, burst lengths are fixed at four. Twelve chip selects SCS# lines allow a maximum of three rows of single-sided SDRAM DIMMs and six rows of double-sided SDRAM DIMMs. The MCH's system memory controller targets CAS latencies of 2 and 3 clocks for SDRAM. The MCH provides refresh functionality with a programmable rate (normal SDRAM rate is 1 refresh/15.6 us).
5.2.2
Memory Organization and Configuration
In the following discussion the term row refers to a set of memory devices that are simultaneously selected by a SCS# signal. The MCH supports a maximum of 6 rows of memory. For the purposes of this discussion, a "side" of a DIMM is equivalent to a "row" of SDRAM devices.
Table 12. Supported DIMM Configurations
Density Device Width Single \ Double 168 pin SDR DIMMs X8 SS/DS 64 MB / 128 MB 64 Mbit X16 SS/DS 32 MB / 64 MB X8 SS/DS 128 MB / 256 MB 128 Mbit X16 SS/DS 64 MB / 128 MB X8 SS/DS 256 MB / 512 MB 256 Mbit X16 SS/DS 128 MB / 256 MB 512 Mbit X8 SS/DS 512 MB / 1024 MB X16 SS/DS 256 MB / 512 MB
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5.2.2.1
Configuration Mechanism For DIMMs
Detection of the type of SDRAM installed on the DIMM is supported via a Serial Presence Detect mechanism as defined in the JEDEC 168-pin DIMM specification. This uses the SCL, SDA and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special programmable modes are provided on the MCH for detecting the size and type of memory installed. Type and size detection must be done via the serial presence detection pins.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the MCH SDRAM registers must be initialized. The MCH must be configured for operation with the installed memory types. Detection of memory type and size is accomplished via the System Management Bus (SMBus) interface on the ICH2. This two-wire bus is used to extract the SDRAM type and size information from the Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin Serial Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0]. Devices on the SMBus bus have a seven-bit address. For the SDRAM DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the system management bus on the ICH2. Thus, data is read from the Serial Presence Detect port on the DIMMs via a series of I/O cycles to the ICH2. BIOS needs to determine the size and type of memory used for each of the rows of memory to properly configure the MCH memory interface.
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details on SMBus Configuration and Serial Present Detect Ports, see the Intel(R) 82801BA I/O Controller Hub 2 (ICH2) and 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) Datasheet.
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence Detect ports are used to determine refresh rate, MA and MD buffer strength, row type (on a row by row basis), SDRAM Timings, row sizes and row page sizes. Table 13 lists a subset of the data available through the on-board Serial Presence Detect ROM on each DIMM. Table 13. Data Bytes on DIMM Used for Programming DRAM Registers
Byte 2 3 4 5 11 12 17 Function Memory type (SDR SDRAM or DDR SDRAM) Number of row addresses, not counting bank addresses Number of column addresses Number of banks of SDRAM (single- or double-sided DIMM) ECC, no ECC Refresh rate Number banks on each device
Table 13 is only a subset of the defined SPD bytes on the DIMMs. These bytes collectively provide enough data for programming the MCH SDRAM registers.
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5.2.3
Memory Address Translation and Decoding
The 845 MCH contains address decoders that translate the address received on the system bus or the hub interface. Decoding and translation of these addresses vary with the four SDRAM types. Also, the number of pages, page sizes, and densities supported vary with the type. In general, the MCH supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM devices. The multiplexed row/column address to the SDRAM memory array is provided by the SBS[1:0] and SMA[12:0] signals. These addresses are derived from the system address bus as defined by Table 14 for SDRAM devices.
Table 14. Address Translation and Decoding
Tech. Configuration Row size Row / Row Addr Page size Column / Col Bank 32 MB 2 KB 64 Mb 2Meg x 8 x 4 bks 64 MB 4 KB 128 Mb 2Meg x 16 x 4bks 64 MB 4 KB 128 Mb 4Meg x 8 x 4bks 128 MB 8 KB 256 Mb 4Meg x 16 x 4 bks 128 MB 4 KB 256 Mb 8Meg x 8 x 4 bks 256 MB 8 KB 512 Mb 8Meg x 16 x 4bks 256 MB 8 KB 512 Mb 16Meg x 8 x 4bks 512 MB 16 KB 13x11x2 13x10x2 13x10x2 13x9x2 12x10x2 12x9x2 12x9x2 12x8x2 Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col 28 14 15 27 26 13 27 14 13 27 26 27 14 13 27 26 26 13 12 26 24 26 14 13 26 25 13 12 24 25 13 12 24 24 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
64 Mb
1Meg x 16 x 4 bks
11
12
24
13 AP 25 AP 25 AP 25 AP 25 AP 25 AP 25 AP 25 AP
14
15
16 10
23 9 23 9 23 9 23 9 23 9 23 9 23 9 23 9
22 8 22 8 22 8 22 8 22 8 22 8 22 8 22 8
21 7 21 7 21 7 21 7 21 7 21 7 21 7 21 7
20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6
19 5 19 5 19 5 19 5 19 5 19 5 19 5 19 5
18 4 18 4 18 4 18 4 18 4 18 4 18 4 18 4
17 3 17 3 17 3 17 3 17 3 17 3 17 3 17 3
14
15 11
16 10 16 10 16 10 16 10 16 10 16 10 16 10
14
15 11
24 12 14
15 11 15 11
24 12 24 12 24 12
15 11 15 11 28 11
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5.2.4
DRAM Performance Description
The overall memory performance is controlled by the DRAM Timing (DRT) Register, pipelining depth used in the MCH, memory speed grade, and the type of SDRAM used in the system. In addition, the exact performance in a system is also dependent on the total memory supported, external buffering, and memory array layout. The most important contribution to overall performance by the system memory controller is to minimize the latency required to initiate and complete requests to memory and to support the highest possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total flight time to complete a cache line request. A complete discussion of performance involves the entire chipset, not just the system memory controller.
5.2.4.1
Data Integrity (ECC)
The MCH supports single-bit Error Correcting Code (or Error Checking and Correcting) and multiple-bit EC (Error Checking) on the system memory interface. The MCH generates an 8-bit code word for each 64-bit QWord of memory. The MCH performs two QWord writes at a time; thus, two 8-bit codes are sent with each write. Since the code word covers a full QWord, writes of less than a QWord require a read-merge-write operation. Consider a DWord write to memory. In this case, when in ECC mode, the MCH reads the QWord where the addressed DWord will be written, merges in the new DWord, generates a code covering the new QWord, and, finally, writes the entire QWord and code back to memory. Any correctable (single-bit) errors detected during the initial QWord read are corrected before merging the new DWord. The MCH also supports EC (Error Checking) data integrity mode. In this mode, the MCH generates and stores a code for each QWord of memory. It then checks the code for reads from memory but does not correct any errors that are found. Thus, the read performance hit associated with ECC is not incurred.
5.3
AGP Interface Overview
The MCH supports 1.5 V AGP 1x/2x/4x devices. The AGP signal buffers are 1.5 V drive/receive (buffers are not 3.3 volt tolerant). The MCH supports 2x/4x source synchronous clocking transfers for read and write data, and sideband addressing. The MCH also support 2x and 4x clocking for Fast Writes initiated from the MCH (on behalf of the processor). AGP PIPE# or SBA[7:0] transactions to system memory do not get snooped and are, therefore, not coherent with the processor caches. AGP FRAME# transactions to system memory are snooped. AGP PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access from an AGP master to the hub interface are also not supported. Only the AGP FRAME memory writes from the hub interface are supported.
5.3.1
AGP Target Operations
As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH supports AGP cycles targeting the interface to system memory only. The MCH supports interleaved AGP PIPE# and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions.
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Table 15. AGP Commands Supported by the Intel MCH When Acting as an AGP Target
AGP Command C/BE[3:0]# Encoding Cycle Destination Read 0000 0000 Hi-Priority Read 0001 0000 Reserved Reserved Write 0010 0011 0100 0100 Hi-Priority Write 0101 0101 System memory Hub interface System memory The Hub interface N/A N/A System memory Hub interface System memory Hub interface MCH Host Bridge Response as PCIx Target Low-priority read Complete with random data High-priority read Complete with random data No response No response Low-priority write Cycle goes to DRAM with byte enables inactive High-priority write Cycle goes to DRAM with byte enables inactive; does not go to the hub interface No response No response Low-priority read Complete locally with random data; does not go to the hub interface High-priority read Complete with random data Complete with QW of random data No response No response; Flag inserted in MCH request queue No response No response No response
(R)
Reserved Reserved Long Read
0110 0111 1000
N/A N/A System memory Hub interface
Hi-Priority Long Read
1001
System memory Hub interface
Flush Reserved Fence Reserved Reserved Reserved
1010 1011 1100 1101 1110 1111
MCH N/A MCH N/A N/A N/A
NOTES: 1. N/A refers to a function that is not applicable
As a target of an AGP cycle, the MCH supports all the transactions targeting system memory (summarized in Table 15). The MCH supports both normal and high-priority read and write requests. The MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles do not require coherency management and all AGP initiator accesses to system memory, using AGP PIPE# or SBA protocol, are treated as non-snoopable cycles. These accesses are directed to the AGP aperture in system memory that is programmed as either uncacheable (UC) memory or write combining (WC) in the processor's MTRRs.
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5.3.2
AGP Transaction Ordering
The MCH observes transaction ordering rules as defined by the AGP Interface Specification, Revision 2.0.
5.3.3
AGP Signal Levels
The 4x data transfers use 1.5 V signaling levels as described by the AGP Interface Specification, Revision 2.0. The MCH supports 1x/2x data transfers using 1.5 V signaling levels.
5.3.4
4x AGP Protocol
In addition to the 1x and 2x AGP protocol, the MCH supports 4x AGP read and write data transfers and 4x sideband address generation. The 4x operation is compliant with the AGP Interface Specification, Revision 2.0. The MCH indicates that it supports 4x data transfers via bit 2 of the AGPSTAT.RATE field. When bit 2 of the AGPCMD.DRATE field is set to 1 during system initialization, the MCH performs AGP read/write data transactions using 4x protocol. This bit is not dynamic. Once this bit is set during initialization, the data transfer rate must not be changed. The 4x data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4x data transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred on every 66 MHz clock edge. The minimum throttleable block size remains four 66 MHz clocks (64 bytes of data are transferred per block). Three additional signal pins are required to implement the 4x data transfer protocol. These signal pins are complimentary data transfer strobes for the AD bus (2) and the SBA bus (1).
5.3.5
Fast Writes
The MCH supports 2x and 4x Fast Writes from the MCH to the graphics controller on AGP. Fast Write operation is compliant with Fast Writes as currently described in the AGP Interface Specification, Revision 2.0. To use the Fast Write protocol, both AGPCTRL.FWCE and AGPCMD.FWPE must be set to 1. AGPCTRL.FWCE is set to 0 by default. When this bit is set to 1, the MCH indicates that it supports Fast Writes through AGPSTAT.FW. When both AGPCMD.FWEN and AGPCTRL.FWCE are set to 1, the MCH uses Fast Write protocol to transfer memory write data to the AGP master. Memory writes originating from the processor or from the hub interface use the Fast Write protocol when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the bits set in the AGPCMD.DRATE field (bits [2:0]). If bit 2 of the AGPCMD.DRATE field is 1, the data transfers occur using 4x strobing. If bit 1 of AGPCMD.DRATE field is 1, the data transfers occur using 2x strobing. If bit 0 of AGPCMD.DRATE field is 1, Fast Writes are disabled and data transfers occur using standard PCI protocol. Note that only one of the three DRATE bits can be set by initialization software (Table 16).
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Table 16. Data Rate Control Bits
AGPCNTL .FWCE 0 1 1 1 AGPCMD. FWPE 0 1 1 1 AGPCMD. DRATE [bit 2] X 0 0 1 AGPCMD. DRATE [bit 1] X 0 1 0 AGPCMD. DRATE [bit 0] X 1 0 0 MCH =>AGP Master Write Protocol 1x 1x 2x strobing 4x strobing
5.3.6
AGP FRAME# Transactions on AGP
The MCH accepts and generates AGP FRAME# transactions on the AGP bus. The MCH guarantees that AGP FRAME# accesses to system memory are kept coherent with the processor caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
MCH Initiator and Target Operations
Table 17 summarizes MCH target operation for AGP FRAME# initiators. The cycles can be either destined to system memory or the hub interface. Table 17. PCI Commands Supported by the Intel MCH (When Acting as a FRAME# Target)
PCI Command C/BE[3:0]# Encoding Interrupt Acknowledge Special cycle I/O Read I/O Write Reserved Reserved Memory Read 0000 0001 0010 0011 0100 0101 0110 0110 Memory Write 0111 0111 Reserved Reserved Configuration Read Configuration Write Memory Read Multiple 1000 1001 1010 1011 1100 1100 Intel(R) MCH Cycle Destination N/A N/A N/A N/A N/A N/A System memory Hub interface System memory Hub interface N/A N/A N/A N/A System memory Hub interface Response as a FRAME# Target No response No response No response No response No response No response Read No response Posts data No response No response No response No response No response Read No response
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PCI Command
C/BE[3:0]# Encoding
Intel(R) MCH Cycle Destination N/A System Memory Hub interface System memory Hub interface Response as a FRAME# Target No response Read No response Posts data Posts Data
Dual Address Cycle Memory Read Line
1101 1110 1110
Memory Write and Invalidate
1111 1111
NOTES: 1. N/A refers to a function that is not applicable
As a target of an AGP FRAME# cycle, the MCH only supports the following transactions: * Memory Read, Memory Read Line, and Memory Read Multiple. These commands are supported identically by the MCH. The MCH does not support reads of the hub interface bus from AGP. * Memory Write and Memory Write and Invalidate. These commands are aliased and processed identically. * Other Commands. Other commands (e.g., I/O R/W and Configuration R/W) are not supported by the MCH as a target and result in master abort. * Exclusive Access. The MCH does not support PCI locked cycles as a target. * Fast Back-to-Back Transactions. The MCH, as a target, supports fast back-to-back cycles from an AGP FRAME# initiator. As an initiator of AGP FRAME# cycle, the MCH only supports the following transactions: * Memory Read and Memory Read Line. MCH supports reads from host to AGP. MCH does not support reads from the hub interface to AGP. * Memory Read Multiple. This command is not supported by the MCH as an AGP FRAME# initiator. * Memory Write. The MCH initiates AGP FRAME# cycles on behalf of the host or the hub interface. As an initiator, the MCH does not issue Memory Write and Invalidate cycles. The MCH does not support write merging or write collapsing. The MCH allows non-snoopable write transactions from the hub interface to the AGP bus. * I/O Read and Write. I/O read and write cycles from the host are sent to the AGP bus. The I/O base and limit address range for the AGP bus are programmed in the configuration registers. All other accesses that do not correspond to this programmed address range are forwarded to the hub interface. * Exclusive Access. The MCH does not issue a locked cycle on the AGP bus on behalf of either the host or the hub interface. The hub interface and host locked transactions to AGP are initiated as unlocked transactions by the MCH on the AGP bus. * Configuration Read and Write. Host configuration cycles to AGP are forwarded as Type 1 configuration cycles. * Fast Back-to-Back Transactions. The MCH, as an initiator, does not perform fast back-toback cycles.
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MCH Retry/Disconnect Conditions
The MCH generates retry/disconnect according to the AGP Interface Specification, Revision 2.0 rules when being accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP FRAME#-to-system memory read cycle is retried by the MCH, it is processed internally as a delayed transaction. The MCH supports the delayed transaction mechanism on the AGP target interface for the transactions issued using AGP FRAME# protocol. This mechanism is compatible with the PCI Local Bus Specification, Revision 2.1. The process of latching all information required to complete the transaction, terminating with Retry, and completing the request without holding the master in wait-states is called a delayed transaction. The MCH latches the address and command when establishing a delayed transaction. The MCH generates a delayed transaction on the AGP only for AGP FRAME# to system memory read accesses. The MCH does not allow more than one delayed transaction access from AGP at any time.
5.4
Power and Thermal Management
An 845 chipset platform is compliant with the following specifications: * APM, Revision 1.2 * ACPI, Revision 1.0b * PCI Power Management, Revision 1.0 * PC '99, Revision 1.0 * PC '99A * PC '01, Revision 1.0
5.4.1
Processor Power State Control
* C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is deasserted, and the processor core is active. The processor can service snoops and maintain cache coherency in this state.
* Stop-Grant State: This function can be enabled or disabled via a configuration bit. When this function is enabled, STPCLK# is asserted to place the processor into the C2 state with a programmable duty cycle. This is an ACPI defined function but BIOS or APM (via BIOS) can use this facility.
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5.4.2
Sleep State Control
* S0 (Awake): In this state all power planes are active. All of the ACPI software "C" states are embedded in this state. * S1: The recommended implementation of S1 state is the same as C2 state (Stop Grant), which is entered by the assertion of the STPCLK# signal from the ICH2 to the processor. A further power saving can be achieved by asserting processor SLP# from the ICH2. This puts the processor into Sleep State. * S2: ACPI S2 state is not supported in the 845 chipset desktop platform. * S3 (Suspend To RAM (STR)): The next level of power reduction occurs when the clock synthesizers and main power planes (ICH2, MCH, and the processor) are shut down but the system memory plane and the ICH2 resume well remain active. This is the Suspend-to-RAM (STR) state. All clocks from synthesizers are shut down during the S3 state. * S4 and S5 (Suspend To Disk (STD), Soft Off): The next level of power reduction occurs when the memory power and MCH are shut down in addition to the clock synthesizers, ICH2, and the processor power planes. The ICH2 resume well is still powered. * G3 (Mechanical Off): In this state only the RTC well is powered. The system can only reactivate when the power switch is returned to the "On" position.
5.5
Intel(R) MCH Clocking
The 845 chipset is supported by the CK_408 compliant clock synthesizer. For details on clocking, refer to the Intel(R) Pentium 4 Processor in a 478 Pin Package and Intel(R) 845 Chipset Platform Design Guide.
5.6
Intel(R) MCH System Reset and Power Sequencing
For details on MCH system reset and power sequencing, refer to the Intel(R) Pentium 4 Processor in a 478 Pin Package and Intel(R) 845 Chipset Platform Design Guide.
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Electrical Characteristics
This chapter contains the absolute maximum operating ratings, power characteristics, and DC characteristics for the 82845 MCH.
6.1
Absolute Maximum Ratings
Table 18 lists the MCH's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the DC tables.
Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operating beyond the "operating conditions" is not recommended and extended exposure beyond "operating conditions" may affect reliability. Table 18. Absolute Maximum Ratings
Symbol Tstorage VCC1_5 VCC1_8 VCCSM VTT Parameter Storage Temperature 1.5 V Supply Voltage with respect to VSS 1.8 V Supply Voltage with respect to VSS 3.3 V Supply Voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Min -55 -0.72 -0.88 -2.83 -0.55 Max 150 2.3 2.69 6.3 2.3 Unit C V V V V Notes
6.2
Power Characteristics
Symbol IVTT IVCC1_5_CORE IVCC1_5_AGP IVCC1_8 IVCCSM ISUS_3.3 Parameter MCH VTT supply current 1.5 V core supply current 1.5 V AGP supply current 1.8 V hub interface supply current 3.3 V system memory supply current 3.3 V standby supply current HVREF, AGPREF, HI_REF, SDREF supply current Min Typ Max 2.4 1.5 0.37 0.20 2.0 25 10 Unit A A A A A mA mA 1 1 Notes
Table 19. Power Characteristics
NOTES: 1. These current levels can happen simultaneously, and can be summed into one supply.
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6.3
Signal Groups
The signal description includes the type of buffer used for the particular signal: AGTL+ AGP Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The MCH integrates most AGTL+ termination resistors. AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. Hub Interface 1.8 V CMOS buffers. System memory 3.3 V CMOS buffers.
HI CMOS SM CMOS Table 20. Signal Groups
Signal Group (a)
Signal Type AGTL+ I/O
Signals ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#, DRDY#, HA[31:3]#, HADSTB[1:0] #, HD[63:0]#, HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, HITM#, HREQ[4:0]# BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]# HLOCK# HVREF, HSWING[1:0] AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], G_C/BE[3:0]#, G_PAR PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#, G_REQ# ST[2:0], G_GNT# AGPREF HI_[10:0], HI_STB, HI_STB# HI_REF SDQ[63:0], SCB[7:0] SCS[11:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#, SCKE[5:0], SCK[11:0], RDCLKO RDCLKI SDREF TESTIN# RSTIN# (3.3V) VTT
(b) (c) (d) (e)
AGTL+ Output AGTL+ Input Host Reference Voltages AGP I/O
(f) (g) (h) (i) (j) (k) (l) (m) (n) (o) (p) (r)
AGP Input AGP Output AGP Reference Voltage Hub Interface's CMOS I/O Hub Interface Reference Voltage SDRAM CMOS I/O SDRAM CMOS Output SDRAM CMOS Input SDRAM Reference Voltage CMOS Input CMOS Input AGTL+ Termination Voltage
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Signal Group (s) (t) (u) (v) (w)
Signal Type 1.5 V Core and AGP Voltage 1.8 V Hub Interface Voltage 3.3 V PC133 SDRAM I/O Voltage CMOS Clock Input CMOS Clock Input VCC1_5 VCC1_8 VCCSM 66IN BCLK, BCLK#
Signals
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6.4
DC Characteristics
Table 21. DC Characteristics
Symbol Signal Group Parameter Min Typ Max Unit Notes
I/O Buffer Supply Voltage VCCSM VCC1_8 VCC1_5 VTT (u) (t) (s) (r) PC133 SDRAM I/O Voltage 1.8V I/O Supply Voltage Core and AGP Voltage Host AGTL+ Termination Voltage 3.135 1.71 1.425 N/A 3.3 1.8 1.5 N/A 3.465 1.89 1.575 1.75 V V V V
Reference Voltages HVREF (d) Host Address and Data Reference Voltage Host Compensation Reference Voltage Hub Interface Reference Voltage SDRAM Reference Voltage AGP Reference Voltage (2/3 x VTT) - 2% 2/3 x VTT (2/3 x VTT) + 2% V
HSWING
(d)
(1/3 x VTT) - 2%
1/3 x VTT
(1/3 x VTT) + 2%
V
HI_REF SDREF AGPREF
(j) (n) (h)
0.48 x VCC1_8 0.49 x VCCSM 0.48 x VCC1_5
1/2 x VCC1_8 1/2 x VCCSM 1/2 x VCC1_5
0.52 x VCC1_8 0.51 x VCCSM 0.52 x VCC1_5
V V V
System Bus Interface VIL VIH VOL VOH IOL (a,c) (a,c) (a,b) (a,b) (a,b) Host AGTL+ Input Low Voltage Host AGTL+ Input High Voltage Host AGTL+ Output Low Voltage Host AGTL+ Output High Voltage Host AGTL+ Output Low Current VTT-0.1 VTTmax / 0.75Rtt (2/3 x VTT) + 0.1 (1/3 x VTT) + 0.1 (2/3 x VTT) - 0.1 V V V V mA Rttmin = 45 Rtttyp = 50 Rttmax = 55 VOLILEAK
(a,c)
Host AGTL+ Input Leakage Current Host AGTL+ Input Capacitance 1.0
15
A
CPAD
(a,c)
pF
3.3 V Interface VIL VIH VOL VOH IOL IOH ILEAK (k,m,p) (k,m,p) (k,l) (k,l) (k,l) (k,l) (k,m,p) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current -4 100 2.4 4 SDREF + 2.0 0.4 SDREF - 2.0 V V V V mA mA A @VOL_S max @VOH_S max 0122
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Symbol
Signal Group (k,m,p)
Parameter
Min
Typ
Max
Unit
Notes
CI/0
Input Capacitance
4.65
5.37
pF
1.5 V Interface VIL VIH VOL VOH IOL IOH ILEAK CIN (e,f) (e,f) (e,g) (e,g) (e,g) (e,g) (e,f) (e,f) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Input Capacitance 1.32 -0.2 15 1.92 0.85 x VCC1_5 1 0.6 x VCC1_5 0.15 x VCC1_5 0.4 x VCC1_5 V V V V mA mA A pF @VOL_A max @VOH_A max 01.8 V Interface VIL VIH VOL VOH IOL IOH ILEAK CIN Clock Signals VIL VIH CIN VIL VIH VCROSS CIN (v) (v) (v) (w) (w) (w) (w) Input Low Voltage Input High Voltage Input Capacitance Input Low Voltage Input High Voltage Crossing Voltage Input Capacitance 0.660 0.45 x (VIH - VIL) 0.94 2.4 1.2 0 0.710 0.850 1.4 0.8 V V pF V V V pF (i,o) (i,o) (i,o) (i,o) (i,o) (i,o) (i,o) (i,o) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Input Leakage Current Input Capacitance 2.58 -1 -150, +15 3.17 0.9 x VCC1_8 1 HI_REF + 0.15 0.1 x VCC1_8 HI_REF - 0.15 V V V V mA mA A pF IOL= 1 mA IOH = 1 mA @VOL_HI max @VOH_HI max 00.5 x (VIH - VIL) 0.55 x (VIH - VIL) 1.1
RSTIN# Signals VIL VIH ILEAK (p) (p) (p) Input Low Voltage Input High Voltage Input Leakage Current 2.0 100 0.8 V V A 0Intel 82845 MCH for SDR Datasheet
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Ballout and Package Information
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Ballout and Package Information
This chapter provides the MCH ballout and package information. The ballout footprint is shown in Figure 6 and Figure 7. These figures represent the ballout organized by ball number. Table 22 provides the MCH ballout listed alphabetically by signal name. The following notes apply to the ballout. Note: NC = No Connect. Note: RSVD = These pins should not be connected and should be allowed to float. Note: VSS = Connect to ground.
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Figure 6. Intel 82845 MCH Ballout Diagram (Top View--Left Side)
29 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 29 28
VCCSM SDQ34 SDQ2 VSS SDQ33 VCCSM SDQ32 VSS SMRCOMP VCC1_8 HI_6 VSS HI_9 VCC1_5 G_AD1 VSS G_AD7 VCC1_5 G_DEVSEL# VSS G_AD18 VCC1_5 AD_STB1# VSS SBA4 VCC1_5 SBA0 SBA2
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28
27
VSS SBA1 SBA3 SB_STB SBA5 NC AD_STB1 G_AD20 G_AD21 G_AD16 G_IRDY# G_AD9 G_AD6 G_AD5 G_AD0 HLRCOMP HI_2 HI_8 HI_7 VSS RSTIN# RSVD SWE# SDQ0 SDQ1 SDQ35 SDQ3 SDQ36 VSS
26
25
VCC1_5 G_GNT#
24
23
VTT VSS
22
21
VTT VSS
20
19
VTT VSS
18
17
VSS HD61#
16
15
VSS HD57#
ST2 SB_STB# VCC1_5 NC VSS G_AD22 VCC1_5 G_AD17 VSS G_AD8 VCC1_5 G_AD4 VSS HI_REF VCC1_8 HI_4 VSS VCCSM VSS TESTIN# VSS RSVD VSS SDQ4 RSVD
ST0 VSS SBA7 GRCOMP G_AD28 G_AD19 G_AD26
G_REQ# ST1 SBA6 G_AD31 G_AD29 G_AD27 G_AD25
VTT VCC1_5 WBF# VCC1_5 VSS G_AD24 G_C/BE3# G_AD23 G_STOP# G_C/BE1# G_AD11 G_AD10 AD_STB0# HI_3 VCC1_8 VSS VCCSM RSVD SCS1# SCS0# SRAS# SDQ8 SDQ41 VCCSM RSVD SDQ9 VSS
VSS PIPE# RBF# VSS G_AD30 VSS VCC1_5 VSS VCC1_5 VSS VCC1_5 VSS VCC1_5 66IN VSS VCC1_8 VSS VCCSM VSS VCCSM SMA0 VCCSM SDQ43 SDQ42 SDQ10
VTT VSS VTT VCC1_5 VSS VCC1_5 AGPREF
VSS VTT VSS VTT VSS VTT
VTT VSS VTT VSS VTT VSS
VSS VTT VSS VTT VSS VTT
HD56# VSS CPURST# HD62# HD58# HVREF
HD55# HD59# HD63# VSS
HD54# VSS HD60# DBI3#
HDSTBP3# HDSTBN3# VSS VSS
G_C/BE2# G_FRAME# G_PAR G_C/BE0# G_AD14 G_AD2 G_AD3 HI_0 HI_STB HI_5 VCC1_8 RSVD SCAS# SCS9# SCS8# SDQ37 SDQ5 VCCSM SDQ38 SDQ6 VCCSM G_TRDY# G_AD15 G_AD13 G_AD12 AD_STB0 HI_1 HI_STB# HI_10 VSS VCCSM SCS4# VCCSM SCS5# VSS SDQ39 SDQ7 SDQ40
VSSA1 VCCA1 VSS VCC1_5 VSS
VCC1_5 VSS VCC1_5 VSS VCC1_5
VSS VCC1_5 VSS VCC1_5 VSS
SDREF VSS SMA3 SMA2 SMA1 VSS SDQ11 SDQ44 VCCSM VCCSM SMA5 VSS SMA4 SDQ12 SDQ45 VSS SMA8 SMA7 SMA6 VCCSM SDQ13 RSVD VSS VCCSM SMA9 VCCSM SDQ47 SDQ46 SDQ14 VSS SBS1 SBS0 SMA10 VSS SDQ15 SCB4 VCCSM VCCSM SCK8 VSS SCB1 SCB5 SCB0 VSS SCK4 SCK9 SMA11 VCCSM SCB2 SCB6 VSS
27
26
25
24
23
22
21
20
19
18
17
16
15
NOTES: 1. NC = No Connect. 2. RSVD = These pins should not be connected and should be allowed to float. 3. VSS = Connect to ground.
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Figure 7. Intel 82845 MCH Ballout Diagram (Top View--Right Side)
14 13 VSS HD49# HD52# HD51# HD53# VSS HD50# VSS HD48# VSS HD46# HSWNG1 HRCOMP1 VSS HD45# HD47# HD40# VSS HD33# VSS 12 11 VSS HD44# HD42# VSS HDSTBN2# HDSTBP2# HD32# HVREF HD43# HD41# HD36# VSS HD39# VSS 10 9 VSS DBI2# HD38# VSS HD34# HD37# HD35# VSS VTT HD27# HD30# HD18# VSS HD14# VTT VSS HVREF VSS VSS VCC1_5 VSS VCC1_5 VSS VCC1_5 VSSA0 VCCA0 VSS VCC1_5 VSS VTT VSS HVREF VSS VSS VTT VSS BCLK# SDREF VCCSM SCK5 VCCSM SDQ48 SCB3 SCB7 VSS SCK1 SCK0 SDQ17 VSS SDQ49 SDQ16 VCCSM 14 13 12 VCCSM SMA12 VSS SDQ50 RSVD SDQ18 VSS SCKE4 SDQ51 SDQ20 VCCSM SDQ52 SDQ19 VSS 11 10 VCCSM SCKE2 VCCSM SDQ53 SDQ54 SDQ21 VSS SCKE0 SDQ22 SDQ56 VSS SDQ23 SDQ55 VCCSM 9 8 BCLK VCCSM SCS3# VSS SDQ24 SDQ57 RSVD 8 7 VSS HD24# HD28# VSS HD29# HD19# 6 5 VSS HD31# HD16# VSS HD23# DBI0# HD5# HD1# HD2# HIT# HLOCK# DBSY# HREQ3# HA4# HADSTB0# HA12# HA28# HA24# HA21# VSS VCCSM SCK10 SCK11 SCKE3 SCKE5 VSS RSVD SDQ28 VCCSM 6 5 4 DBI1# HD26# VSS 4 3 VSS HD25# HD22# HD21# HD8# HD15# VSS HD20# HD17# VSS 2 1 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 2 1
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HDSTBP1# HDSTBN1# HD10# HD11# HD9# HSWNG0 BPRI# RS1# BR0# HTRDY# HREQ1# HREQ2# HA8# HA15# HVREF HA31# VSS VCCSM SCS6# SCS2# SCS7# SDQ25 VCCSM SDQ26 SDQ58 VSS 7 VSS HD12# VSS HD7# VSS RS2# VSS HREQ0# VSS HA11# VSS HADSTB1# HA30# VSS VCCSM VSS SCS11# SCS10# VCCSM SDQ59 SDQ27 SDQ60
HDSTBN0# HDSTBP0# VSS HD4# VSS DEFER# VSS DRDY# VSS HA3# VSS HA10# VSS HA18# VSS HA17# VSS HA27# VCCSM SCKE1 VSS SDQ29 SDQ61 HD13# HD3# HD6# HITM# BNR# ADS# HA6# HA5# HA7# HA13# HA16# HA19# HA20# HA22# HA25# RDCLKO RDCLKIN SCK6 SCK7 SDQ63 SDQ30 SDQ62 VSS 3 SCK3 SDQ31 VCCSM SCK2 VSS HA29# VCCSM HA23# VSS HA26# VSS HA14# VSS HA9# VSS HREQ4# VSS RS0# VSS HD0# VSS HRCOMP0 VSS
NOTES: 1. NC = No Connect. 2. RSVD = These pins should not be connected and should be allowed to float. 3. VSS = Connect to ground.
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Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name
Signal Name 66IN AD_STB0 AD_STB0# AD_STB1 AD_STB1# ADS# AGPREF BCLK# BCLK BNR# BPRI# BR0# CPURST# DBSY# DEFER# DBI0# DBI1# DBI2# DBI3# DRDY# G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 P22 R24 R23 AC27 AC28 V3 AA21 K8 J8 W3 Y7 V7 AE17 V5 Y4 AD5 AG4 AH9 AD15 V4 R27 R28 T25 R25 T26 T27 U27 U28 V26 V27 T23 U23 T24 U24 Ball # Signal Name G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31 G_C/BE0# G_C/BE1# G_C/BE2# G_C/BE3# G_DEVSEL# G_FRAME# G_GNT# G_IRDY# G_PAR G_REQ# G_STOP# G_TRDY# GRCOMP HA3# HA4# HA5# U25 V24 Y27 Y26 AA28 AB25 AB27 AA27 AB26 Y23 AB23 AA24 AA25 AB24 AC25 AC24 AC22 AD24 V25 V23 Y25 AA23 W28 Y24 AH25 W27 W25 AG24 W23 W24 AD25 T4 T5 T3 Ball #
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Signal Name HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HADSTB0# HADSTB1# HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# U3 R3 P7 R2 P4 R6 P5 P3 N2 N7 N3 K4 M4 M3 L3 L5 K3 J2 M5 J3 L2 H4 N5 G2 M6 L7 R5 N6 AA2 AB5 AA5 AB3 AB4 AC5 AA3 AA6
Ball #
Signal Name HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# AE3 AB7 AD7 AC7 AC6 AC3 AC8 AE2 AG5 AG2 AE8 AF6 AH2 AF3 AG3 AE5 AH7 AH3 AF4 AG8 AG7 AG6 AF8 AH5 AC11 AC12 AE9 AC9 AE10 AD9 AG9 AC10 AE12 AF10 AG11 AG10
Ball #
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Signal Name HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HDSTBN0# HDSTBP0# HDSTBN1# HDSTBP1# HDSTBN2# HDSTBP2# HDSTBN3# HDSTBP3# HI_0 HI_1 HI_2 HI_3 HI_4 HI_5 HI_6 HI_7 AH11 AG12 AE13 AF12 AG13 AH13 AC14 AF14 AG14 AE14 AG15 AG16 AG17 AH15 AC17 AF16 AE15 AH17 AD17 AE16 AD4 AD3 AE6 AE7 AE11 AD11 AC15 AC16 P25 P24 N27 P23 M26 M25 L28 L27
Ball #
Signal Name HI_8 HI_9 HI_10 HI_REF HI_STB HI_STB# HIT# HITM# HLOCK# HLRCOMP HRCOMP0 HRCOMP1 HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HSWNG0 HSWNG1 HTRDY# HVREF NC PIPE# RBF# RDCLKIN RDCLKO RS0# RS1# RS2# RSTIN# RSVD SBA0 SBA1 SBA2 SBA3 M27 N28 M24 P26 N25 N24 Y5 Y3 W5 P27 AC2 AC13 U6 T7 R7 U5 U2 AA7 AD13 U7
Ball #
M7, R8, Y8, AB11, AB17 AD26, AD27 AF22 AE22 G3 H3 W2 W7 W6 J27 B19, C5, C8, C23, C26, D12, F26, H27, K23, K25 AH28 AH27 AG28 AG27
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Signal Name SBA4 SBA5 SBA6 SBA7 SB_STB SB_STB# SBS0 SBS1 SCAS# SCK0 SCK1 SCK2 SCK3 SCK4 SCK5 SCK6 SCK7 SCK8 SCK9 SCK10 SCK11 SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 SCS0# SCS1# SCS2# SCS3# SCS4# SCS5# SCS6# SCS7# SCS8# AE28 AE27 AE24 AE25 AF27 AF26 F17 G17 J25 F13 G13 E2 C2 G15 G14 F3 E3 G16 F15 H5 G5 G9 F4 G10 F5 G11 E5 H23 J23 G7 G8 J24 G24 H7 F7 G25
Ball #
Signal Name SCS9# SCS10# SCS11# SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 H25 G6 H6 F27 E27 B28 C27 D26 E25 B25 D24 F23 B23 C22 C21 D20 C19 C18 C17 B13 E13 C12 B11 E11 C10 F9 C9 E8 E7 C7 D6 B5 D4 C3 B2 G28
Ball #
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Signal Name SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SCB0 SCB1 SCB2 SCB3 SCB4 E28 C28 D27 B27 F25 C25 E24 C24 E23 D22 E22 B21 C20 D18 E18 E14 C13 E12 F11 C11 E10 D10 B9 E9 D8 B7 E6 C6 C4 B3 D3 C16 E16 C15 D14 B17
Ball #
Signal Name SCB5 SCB6 SCB7 SDREF SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMRCOMP SRAS# ST0 ST1 ST2 SWE# TESTIN# VCC1_5 D16 B15 C14 J9, J21 G22 E21 F21 G21 E20 G20 E19 F19 G19 G18 E17 E15 G12 J28 G23 AG25 AF24 AG26 G27 H26
Ball #
R22, R29, U22, U26, W22, W29, AA22, AA26, AB21, AC29, AD21, AD23, AE26, AF23, AG29, AJ25 N14, N16, P13, P15, P17, R14, R16, T15, U14, U16 T17 T13 L25, L29, M22, N23, N26 A5, A9, A13, A17, A21, A25, C1, C29, D7, D11, D15, D19, D23, D25, F6, F10, F14, F18, F22, G1, G4, G29, H8, H10, H12, H14, H16, H18, H20, H22, H24, J5, J7, K6, K22, K24, K26, L23
VCC1_5 VCCA1 VCCA0 VCC1_8 VCCSM
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Signal Name VSS
Ball # A3, A7, A11, A15, A19, A23, A27, D5, D9, D13, D17, D21, E1, E4, E26, E29, F8, F12, F16, F20, F24, G26, H9, H11, H13, H15, H17, H19, H21, J1, J4, J6, J22, J26, J29, K5, K7, K27, L1, L4, L6, L8, L22, L24, L26, M23, N1, N4, N8, N13, N15, N17, N22, N29, P6, P8, P14, P16, R1, R4, R13, R15, R17, R26, T6, T8, T14, T16, T22, U1, U4, U15, U29, V6, V8, V22, W1, W4, W8, W26, Y6, Y22, AA1, AA4, AA8, AA29, AB6, AB9, AB10, AB12, AB13, AB14, AB15, AB16, AB19, AB22, AC1, AC4, AC18, AC20, AC21, AC23, AC26, AD6, AD8, AD10, AD12, AD14, AD16, AD19, AD22, AE1, AE4, AE18, AE20, AE29, AF5, AF7, AF9, AF11, AF13, AF15, AF17, AF19, AF21, AF25, AG1, AG18, AG20, AG22, AH19, AH21, AH23, AJ3, AJ5, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ27
Signal Name VSSA1 VSSA0 VTT U17 U13
Ball #
M8, U8, AA9, AB8, AB18, AB20, AC19, AD18, AD20, AE19, AE21, AF18, AF20, AG19, AG21, AG23, AJ19, AJ21, AJ23 AE23
WBF#
NOTES: 1. NC = No Connect. 2. RSVD = These pins should not be connected and should be allowed float. 3. VSS = Connect to ground.
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7.1
Package Mechanical Information
This section provides the MCH package mechanical dimensions. The package is a 593 ball FC-BGA.
Figure 8. Intel MCH FC-BGA Package Dimensions (Top and Side View)
Top View
37.50 33.90 16.95
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16.95
37.50 33.90
9.67 36.28
0.61
Side View
Substrate 0.600 0.100 Die See D etail A 1.100 0.100
A
Detail A 0.74 0.025 Underfill Epoxy
0.152
0.10 0.025 Units = M illim eters
Die Solder Bum ps
pkg_olga_593_top-side
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Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View)
35.560 17.780 1.270 AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 22 28 10 11 12 13 14 15 16 17 18 20 23 24 25 26 27 29 21 19 1.270 17.780 35.560
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Note: All dim ensions are in m illim eters
pkg-MC H_olga_593_Bot
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8
Testability
In the MCH, testability for Automated Test Equipment (ATE) board-level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it (see Figure 10). Figure 10. XOR Tree Chain
VCC1_8
XOR Out
Input
Input
Input
Input
Input
xor.vsd
The algorithm used for in-circuit test is as follows: * Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain being tested. * Toggle pins one at a time (starting from the first pin in the chain and continuing to the last pin) from its initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
8.1
XOR Test Mode Initialization
XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition of RSTIN#. The signals that need to be pulled are as follows: * G_GNT# = 0 (Global strap enable) * SBA1 = 0 (XOR strap) * ST2 = 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)
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8.2
XOR Chains
Note: RSTIN#, TESTIN#, and all Rcomp buffers are not part of any XOR chain.
Table 23. XOR Chain 0
Chain 0 Ball AE6 AD3 V3 U6 U3 U2 U5 T5 T7 T4 R7 R5 R3 P3 R2 R6 T3 N3 P5 P4 P7 N2 N7 N5 M4 L3 M3 L2 K3 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 Signal Name HDSTBP1# HDSTBP0# ADS# HREQ0# HA6# HREQ4# HREQ3# HA4# HREQ1# HA3# HREQ2# HADSTB0# HA7# HA13# HA9# HA11# HA5# HA16# HA12# HA10# HA8# HA14# HA15# HA28# HA18# HA20# HA19# HA26# HA22# Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Chain 0 Ball M5 K3 K4 J3 L5 H4 M6 L7 G2 H6 H3 G3 H5 G6 E7 G8 G9 AH28
Element # 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Signal Name HA24# HA23# HA17# HA25# HA21# HA27# HA30# HA31# HA29# SCS11# RDCLKIN RDCLKO SCK10 SCS10# SCS7# SCS3# SCKE0 SBA0
Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
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Table 24. XOR Chain 1
Chain 1 Ball N6 H7 G10 G5 F4 F3 C2 B2 E2 D3 E3 G7 C3 E5 F7 D4 C4 C5 E6 D6 B3 C6 B5 C7 B7 E8 C8 C9 D8 E10 B9 E11 E9 AH27 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name HADSTDB1# SCS6# SCKE2 SCK11 SCKE1 SCK6 SCK3 SDQ31 SCK2 SDQ63 SCK7 SCS2# SDQ30 SCKE5 SCS7# SDQ29 SDQ61 RSVD SDQ59 SDQ27 SDQ62 SDQ60 SDQ28 SDQ26 SDQ58 SDQ24 RSVD SDQ23 SDQ57 SDQ53 SDQ5 SDQ20 SDQ56 SBA1 Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
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Table 25. XOR Chain 2
Chain 2 Ball D10 C10 C11 F9 B11 B13 G11 C12 F11 C13 D12 E12 E13 G14 G13 F15 E15 G16 E16 E18 F17 F19 G18 G20 G19 F21 G21 E22 G24 G23 G25 H23 J25 AG28 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name SDQ54 SDQ21 SDQ52 SDQ22 SDQ19 SDQ16 SCKE4 SDQ18 SDQ51 SDQ49 RSVD SDQ50 SDQ17 SCK5 SCK1 SCK9 SMA11 SCK8 SDQ65 SDQ47 SBS0 SMA7 SMA9 SMA5 SMA8 SMA2 SMA3 SDQ43 SCS5# SRAS# SCS8# SCS0# SCAS# SBA2 Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
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Table 26. XOR Chain 3
Chain 3 Ball G10 G12 G15 F13 C14 E14 D14 C15 G17 C16 D16 B15 C17 B17 D18 E17 B19 C18 E19 C19 C20 D20 C21 E20 B21 E21 C22 D22 C24 C23 B23 D24 G22 E23 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name SCKE0 SMA12 SCK4 SCK0 SCB3 SDQ48 SCB7 SCB6 SBCS1 SDQ64 SCB5 SCB5 SDQ15 SCB4 SDQ46 SMA10 RSVD SDQ14 SMA6 SDQ13 SDQ45 SDQ12 SDQ11 SMA4 SDQ44 SMA1 SDQ10 SDQ42 SDQ40 RSVD SDQ9 SDQ7 SMA0 SDQ41 Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Chain 3 Ball B25 C25 C27 D27 B27 C26 F23 E24 E25 E27 N24 R24 AG27
Element # 35 36 37 38 39 40 41 42 43 44 45 46 47
Signal Name SDQ6 SDQ38 SDQ3 SDQ35 SDQ36 RSVD SDQ8 SDQ39 SDQ5 SDQ1 HI_STB# AD_STB SBA3
Note Input Input Input Input Input Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 N/A
Table 27. XOR Chain 4
Chain 4 Ball D26 F25 B28 C28 E28 J24 F26 H25 K25 J23 F27 K23 G28 G27 M27 M24 N28 L28 M25 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Signal Name SDQ4 SDQ37 SDQ2 SDQ3 SDQ33 SCS4# RSVD SCS9# RSVD SCS1# SDQ0 RSVD SDQ32 SWE# HI_8 HI_10 HI_9 HI_6 HI_5 Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Chain 4 Ball N27 M26 N25 L27 P25 P23 P24 R27 R28 U27 R25 T27 T36 U28 R24 V27 T25 U27 T24 U24 U25 T23 V24 U23 AE28
Element # 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Signal Name HI_2 HI_4 HI_STB HI_7 HI_0 HI_3 HI_1 G_ADO G_AD1 G_AD6 G_AD3 G_AD5 G_AD4 G_AD7 AD_STB0 G_AD9 G_AD2 G_AD8 G_AD12 G_AD13 G_AD14 G_AD10 G_AD15 G_AD11 SBA4
Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
Table 28. XOR Chain 5
Chain 5 Ball V25 W28 W25 Y25 W27 V23 Y24 Element # 1 2 3 4 5 6 7 Signal Name G_C/BE0# G_DEVSEL# G_PAR G_C/BE2# G_IRDY# G_C/BE1# G_FRAME# Note Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1
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Chain 5 Ball W24 AE23 W23 AA23 AA28 Y26 Y27 AB27 AB26 AA25 AA24 AA27 AC27 Y23 AC25 AB25 AB23 AB24 AC24 AC22 AB24 AE22 AF24 AF22 AF27 AH25 AG25 AG24 AG26 AH17 AG16 AG17 AC16 AE11 AE27
Element # 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Signal Name G_TRDY# WBF# G_STOP# G_C/BE3# G_AD18 G_AD17 G_AD16 G_AD20 G_AD22 G_AD26 G_AD25 G_AD21 AD_STB1 G_AD23 G_AD28 G_AD19 G_AD24 G_AD31 G_AD29 G_AD30 G_AD27 RBF# ST1 PIPE# SB_STB G_GNT# ST0 G_REQ# ST2 HD61# HD55# HD56# HDSTBP3# HDSTBP2# SBA5
Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
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Table 29. XOR Chain 6
Chain 6 Ball AC27 AF27 AE17 AD17 AE16 AH15 AG15 AF16 AC16 AE15 AG14 AC17 AF14 AE14 AH13 AD15 AG13 AC14 AF12 AG12 AE12 AE13 AH9 AG10 AH11 AG9 AG11 AE11 AF10 AE10 AC12 AC11 AC10 AE9 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name AD_STB1 SB_STB CPURST# HD62# HD63# HD57# HD54# HD59# HDSTBP3# HD60# HD52# HD58# HD51# HD53# HD49# DBI3# HD48# HD50# HD47# HD45# HD40# HD46# DBI2# HD43# HD44# HD38# HD42# HDSTBN2# HD41# HD36# HD33# HD32# HD39# HD34# Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Chain 6 Ball AC9 AD9 AH7 AH5 AG8 Y4 W7 AE24
Element # 35 36 37 38 39 40 41 42
Signal Name HD35# HD37# HD24# HD31# HD27# DEFER# RS1# SBA6
Note Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 N/A
Table 30. XOR Chain 7
Chain 7 Ball AG6 AG5 AG7 AF6 AF8 AE6 AG4 AH3 AE8 AG2 AF4 AH2 AE5 AG3 AF3 AD7 AC7 AC8 AD5 AC6 AE2 AB7 AE3 AD4 Element # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDR Ball name HD29# HD16# HD28# HD19# HD30# HDSTBN1# DBI1# HD25# HD18# HD17# HD26# HD20# HD23# HD22# HD21# HD10# HD11# HD14# DBI0# HD12# HD15# HD9# HD8# HDSTBN0# Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Chain 7 Ball AC3 AB5 AC5 AA6 AA5 AB3 AA3 AB4 AA2 Y5 Y7 W6 Y3 U7 W5 V7 W3 W2 V5 V4 AE25
Element # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 41 43 44 45
SDR Ball name HD13# HD1# HD5# HD7# HD2# HD3# HD6# HD4# HD0# HIT# BPRI# RS2# HITM# HTRDY# HLOCK# BR0# BNR# RS0# DBSY# DRDY# SBA7
Note Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
Initial Logic Level 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N/A
148
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